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authorPuthikorn Voravootivat <puthik@chromium.org>2018-08-31 11:05:40 -0700
committerFurquan Shaikh <furquan@google.com>2018-09-26 21:22:16 +0000
commitaa69e2859df03229e4d48c36d914666544ba8eec (patch)
treef831b150b3d4ac22bc34a64ca1a7e313d6bd3eb6
parent8ac6a19155b2e65dec83032e9b6ce9aa9a9e121b (diff)
downloadcoreboot-aa69e2859df03229e4d48c36d914666544ba8eec.tar.xz
mb/google/poppy/variants/nocturne: Update DPTF settings
The previous does not work well enough when testing with high ambient temperature. Update DPTF settings to make it work better. List of tweaks: 1. Raise DRAM Critical temperature from 48C to 55C Note that there are mechanisms in EC that complement this because of DPTF limitation that we can't have multiple passive temperatures. 2. Lower response time for DRAM temp sensor from 60s to 5s. 3. Increase throttle priority to the charger when DRAM hit passive temperature from 100 to 200. BUG=b:112550414 BRANCH=None TEST=Manually tested by thermal team. Change-Id: Idf7efa76b2c6085cf97aa9f65c6ce066e8cff99a Signed-off-by: Puthikorn Voravootivat <puthik@chromium.org> Reviewed-on: https://review.coreboot.org/28738 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/dptf.asl6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/dptf.asl b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/dptf.asl
index f9773b82da..40c7f6304b 100644
--- a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/dptf.asl
+++ b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/dptf.asl
@@ -30,7 +30,7 @@
#define DPTF_TSR2_SENSOR_ID 3
#define DPTF_TSR2_SENSOR_NAME "DRAM"
#define DPTF_TSR2_PASSIVE 45
-#define DPTF_TSR2_CRITICAL 48
+#define DPTF_TSR2_CRITICAL 55
#define DPTF_TSR3_SENSOR_ID 4
#define DPTF_TSR3_SENSOR_NAME "eMMC"
@@ -56,7 +56,7 @@ Name (DTRT, Package () {
Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
/* CPU Throttle Effect on DRAM (TSR2) */
- Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 },
+ Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 50, 0, 0, 0, 0 },
/* CPU Throttle Effect on eMMC (TSR3) */
Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR3, 100, 600, 0, 0, 0, 0 },
@@ -66,7 +66,7 @@ Name (DTRT, Package () {
Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 },
/* Charger Throttle Effect on DRAM (TSR2) */
- Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 },
+ Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR2, 200, 50, 0, 0, 0, 0 },
#endif
})