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authorBrandon Breitenstein <brandon.breitenstein@intel.com>2017-08-01 11:32:06 -0700
committerMartin Roth <martinroth@google.com>2017-08-11 16:04:42 +0000
commitae1548621acae99b7f7ac4a722607af0a4a0c825 (patch)
treedf032b9479804d2b0ab0452712c24f8858a23e53
parent7c8d331fbb0bb51af441f7e7615be2486e56c0d2 (diff)
downloadcoreboot-ae1548621acae99b7f7ac4a722607af0a4a0c825.tar.xz
soc/cannonlake: Enable SMM code for Cannon Lake
The minimum needed defines are included here and pm.h will be updated when the PMC code for cannonlake is uploaded. Change-Id: Idaf2be1258b3ec71fa449b88516bcb06c730d776 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/20849 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/soc/intel/cannonlake/Kconfig2
-rw-r--r--src/soc/intel/cannonlake/include/soc/pm.h17
-rw-r--r--src/soc/intel/cannonlake/smihandler.c31
3 files changed, 50 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index 471fe6ca78..fa5b8e4823 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -32,6 +32,8 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_RTC
select SOC_INTEL_COMMON_BLOCK_SA
select SOC_INTEL_COMMON_BLOCK_SMBUS
+ select SOC_INTEL_COMMON_BLOCK_SMM
+ select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
select SOC_INTEL_COMMON_BLOCK_TIMER
select SOC_INTEL_COMMON_BLOCK_UART
select SOC_INTEL_COMMON_RESET
diff --git a/src/soc/intel/cannonlake/include/soc/pm.h b/src/soc/intel/cannonlake/include/soc/pm.h
index d69250776c..66541228fe 100644
--- a/src/soc/intel/cannonlake/include/soc/pm.h
+++ b/src/soc/intel/cannonlake/include/soc/pm.h
@@ -20,6 +20,23 @@
#include <arch/acpi.h>
#include <soc/pmc.h>
+#define PM1_EN 0x02
+#define PWRBTN_EN (1 << 8)
+#define GBL_EN (1 << 5)
+#define SMI_EN 0x30
+#define ESPI_SMI_EN (1 << 28)
+#define APMC_EN (1 << 5)
+#define SLP_SMI_EN (1 << 4)
+#define EOS (1 << 1)
+#define GBL_SMI_EN (1 << 0)
+
+
+#define GPE0_EN(x) (0x70 + ((x) * 4))
+#define PME_B0_EN (1 << 13)
+
+#define ENABLE_SMI_PARAMS \
+ (APMC_EN | SLP_SMI_EN | GBL_SMI_EN | ESPI_SMI_EN | EOS)
+
struct chipset_power_state {
uint16_t pm1_sts;
uint16_t pm1_en;
diff --git a/src/soc/intel/cannonlake/smihandler.c b/src/soc/intel/cannonlake/smihandler.c
new file mode 100644
index 0000000000..eb3c5e3b47
--- /dev/null
+++ b/src/soc/intel/cannonlake/smihandler.c
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <intelblocks/smihandler.h>
+
+static smi_handler_t southbridge_smi[SMI_STS_BITS] = {
+ [SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep,
+ [APM_STS_BIT] = smihandler_southbridge_apmc,
+ [PM1_STS_BIT] = smihandler_southbridge_pm1,
+ [GPE0_STS_BIT] = smihandler_southbridge_gpe0,
+ [GPIO_STS_BIT] = smihandler_southbridge_gpi,
+ [ESPI_SMI_STS_BIT] = smihandler_southbridge_espi,
+ [MCSMI_STS_BIT] = smihandler_southbridge_mc,
+ [TCO_STS_BIT] = smihandler_southbridge_tco,
+ [PERIODIC_STS_BIT] = smihandler_southbridge_periodic,
+ [MONITOR_STS_BIT] = smihandler_southbridge_monitor,
+};