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authorSubrata Banik <subrata.banik@intel.com>2019-06-08 20:30:41 +0530
committerSubrata Banik <subrata.banik@intel.com>2019-06-12 02:17:00 +0000
commitb5bea526ec80c0aeccd78a0ece6ac091aa512b54 (patch)
tree1116b9755a49159f2fadee822638cfdef304f2a7
parent70ca84d6e7a2a591ca32c14ca927d9c636ec75d0 (diff)
downloadcoreboot-b5bea526ec80c0aeccd78a0ece6ac091aa512b54.tar.xz
mb/google/hatch: Disable dynamic clock gating for cr50's GPIO
Disable dynamic clock gating for the community cr50's IRQ lives on. That IRQ is pulsed very quickly, and with clock gating enabled pulses tend to be missed. This is expecially true on the default 0.0.22 firmware that cr50 comes with out of the factory. BUG=b:130764684 b:130338605 BRANCH=None TEST=Boot hatch with cr50 "intap" firmware that can vary the pulse width, observe that even with sub-microsecond pulses no IRQs are missed. Change-Id: I34d14fb7cc97e33eecfda2c99cc53a541c87662d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Evan Green <evgreen@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33326 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
-rw-r--r--src/mainboard/google/hatch/variants/baseboard/devicetree.cb4
1 files changed, 3 insertions, 1 deletions
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
index 1123d53734..61b712dbec 100644
--- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
@@ -99,7 +99,9 @@ chip soc/intel/cannonlake
register "gpio_pm[COMM_1]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
register "gpio_pm[COMM_2]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
register "gpio_pm[COMM_3]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
- register "gpio_pm[COMM_4]" = "MISCCFG_GPSIDEDPCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN"
+ # Disable clock gating on this community so that cr50's short irq
+ # pulses won't be missed.
+ register "gpio_pm[COMM_4]" = "0"
device cpu_cluster 0 on
device lapic 0 on end