summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorMike Banon <mikebdp2@gmail.com>2020-02-13 15:45:05 +0000
committerPatrick Georgi <pgeorgi@google.com>2020-02-24 13:55:41 +0000
commitbb45f38eb9d0ecc6f4a1d0ca37c8c52212360c56 (patch)
tree3a8c9447386cc7317f8b761653be54875104a81f
parent6ed9df448b4d025a4caa01b594fca90724eef691 (diff)
downloadcoreboot-bb45f38eb9d0ecc6f4a1d0ca37c8c52212360c56.tar.xz
mb/bap/ode_e20XX: Switch away from ROMCC_BOOTBLOCK
Warning: not tested on hardware. Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I37a1a95bdf07d99916247095a5bc3ac5349cd98f Reviewed-on: https://review.coreboot.org/c/coreboot/+/38869 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/mainboard/bap/ode_e20XX/Kconfig4
-rw-r--r--src/mainboard/bap/ode_e20XX/Kconfig.name4
-rw-r--r--src/mainboard/bap/ode_e20XX/Makefile.inc2
-rw-r--r--src/mainboard/bap/ode_e20XX/bootblock.c (renamed from src/mainboard/bap/ode_e20XX/romstage.c)19
4 files changed, 7 insertions, 22 deletions
diff --git a/src/mainboard/bap/ode_e20XX/Kconfig b/src/mainboard/bap/ode_e20XX/Kconfig
index 2a72debf58..4df74c0c24 100644
--- a/src/mainboard/bap/ode_e20XX/Kconfig
+++ b/src/mainboard/bap/ode_e20XX/Kconfig
@@ -14,14 +14,10 @@
# GNU General Public License for more details.
#
-config BOARD_ODE_E20XX
- def_bool n
-
if BOARD_ODE_E20XX
config BOARD_SPECIFIC_OPTIONS
def_bool y
- #select ROMCC_BOOTBLOCK
select CPU_AMD_AGESA_FAMILY16_KB
select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB
select SOUTHBRIDGE_AMD_AGESA_YANGTZE
diff --git a/src/mainboard/bap/ode_e20XX/Kconfig.name b/src/mainboard/bap/ode_e20XX/Kconfig.name
index 54ddcac682..a482846808 100644
--- a/src/mainboard/bap/ode_e20XX/Kconfig.name
+++ b/src/mainboard/bap/ode_e20XX/Kconfig.name
@@ -1,2 +1,2 @@
-#config BOARD_ODE_E20XX
-# bool"ODE_e20xx"
+config BOARD_ODE_E20XX
+ bool "ODE_e20xx"
diff --git a/src/mainboard/bap/ode_e20XX/Makefile.inc b/src/mainboard/bap/ode_e20XX/Makefile.inc
index 4d8eb8dba0..8747d2fecb 100644
--- a/src/mainboard/bap/ode_e20XX/Makefile.inc
+++ b/src/mainboard/bap/ode_e20XX/Makefile.inc
@@ -14,6 +14,8 @@
# GNU General Public License for more details.
#
+bootblock-y += bootblock.c
+
romstage-y += buildOpts.c
romstage-y += BiosCallOuts.c
romstage-y += OemCustomize.c
diff --git a/src/mainboard/bap/ode_e20XX/romstage.c b/src/mainboard/bap/ode_e20XX/bootblock.c
index c1b96f1273..8744547bfc 100644
--- a/src/mainboard/bap/ode_e20XX/romstage.c
+++ b/src/mainboard/bap/ode_e20XX/bootblock.c
@@ -1,10 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- * Copyright (C) 2015 BAP - Bruhnspace Advanced Projects
- * (Written by Fabian Kunkel <fabi@adv.bruhnspace.com> for BAP)
- *
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
@@ -15,26 +11,17 @@
* GNU General Public License for more details.
*/
-#include <arch/io.h>
#include <amdblocks/acpimmio.h>
-#include <device/pci_ops.h>
-#include <southbridge/amd/agesa/hudson/hudson.h>
-
-#include <northbridge/amd/agesa/state_machine.h>
+#include <bootblock_common.h>
#include <superio/fintek/common/fintek.h>
#include <superio/fintek/f81866d/f81866d.h>
-
#define SERIAL_DEV1 PNP_DEV(0x4e, F81866D_SP1)
-void board_BeforeAgesa(struct sysinfo *cb)
+void bootblock_mainboard_early_init(void)
{
/* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */
- pm_io_write(0xea, 1);
-
- /* Set LPC decode enables. */
- pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
- pci_write_config32(dev, 0x44, 0xff03ffd5);
+ pm_write8(0xea, 0x1);
fintek_enable_serial(SERIAL_DEV1, CONFIG_TTYS0_BASE);
}