Fix many things for via/epia-m700 to build.

Unfortunately it still doesn't.  I think it's close, though.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4397 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

16 files changed, 191 insertions, 180 deletions

diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index 328e3d5e80..ef1130405d 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -1190,6 +1190,11 @@
 #define PCI_DEVICE_ID_VIA_VT8237S_LPC	0x3372
 #define PCI_DEVICE_ID_VIA_VT8237_SATA	0x5372
 #define PCI_DEVICE_ID_VIA_VT8237_VLINK	0x287e
+#define PCI_DEVICE_ID_VIA_VX855_LPC	0x8353
+#define PCI_DEVICE_ID_VIA_VX855_IDE	0x5324
+#define PCI_DEVICE_ID_VIA_VX855_VGA	0x5122
+#define PCI_DEVICE_ID_VIA_VX855_VLINK	0x7409
+#define PCI_DEVICE_ID_VIA_VX855_MEMCTRL	0x3409
 #define PCI_DEVICE_ID_VIA_CN700_AGP	0x0314
 #define PCI_DEVICE_ID_VIA_CN700_ERR	0x1314
 #define PCI_DEVICE_ID_VIA_CN700_HOST	0x2314
diff --git a/src/mainboard/via/epia-m700/Config.lb b/src/mainboard/via/epia-m700/Config.lb
index 77ccb6e703..636f69ef8e 100644
--- a/src/mainboard/via/epia-m700/Config.lb
+++ b/src/mainboard/via/epia-m700/Config.lb
@@ -58,7 +58,7 @@ if CONFIG_USE_DCACHE_RAM
   end
 end
 mainboardinit cpu/x86/16bit/entry16.inc
-ldscript /cpu/via/16bit/entry16.lds
+ldscript /cpu/x86/16bit/entry16.lds
 
 mainboardinit northbridge/via/vx800/romstrap.inc
 ldscript /northbridge/via/vx800/romstrap.lds
diff --git a/src/mainboard/via/epia-m700/acpi_tables.c b/src/mainboard/via/epia-m700/acpi_tables.c
index 709af4b65e..ecb8de48e3 100644
--- a/src/mainboard/via/epia-m700/acpi_tables.c
+++ b/src/mainboard/via/epia-m700/acpi_tables.c
@@ -59,25 +59,6 @@ unsigned long acpi_fill_mcfg(unsigned long current)
 	return current;
 }
 
-unsigned long acpi_create_madt_lapics(unsigned long current)
-{
-	device_t cpu;
-	int cpu_index = 0;
-
-	for (cpu = all_devices; cpu; cpu = cpu->next) {
-		if ((cpu->path.type != DEVICE_PATH_APIC) ||
-		    (cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) {
-			continue;
-		}
-		if (!cpu->enabled)
-			continue;
-		current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current,
-					   cpu_index, cpu->path.apic.apic_id);
-		cpu_index++;
-	}
-	return current;
-}
-
 unsigned long acpi_create_madt_lapic_nmis(unsigned long current, u16 flags,
 					  u8 lint)
 {
diff --git a/src/mainboard/via/epia-m700/cache_as_ram_auto.c b/src/mainboard/via/epia-m700/cache_as_ram_auto.c
index de5acb90bd..8a2c8a0267 100644
--- a/src/mainboard/via/epia-m700/cache_as_ram_auto.c
+++ b/src/mainboard/via/epia-m700/cache_as_ram_auto.c
@@ -208,6 +208,21 @@ static void enable_shadow_ram(void)
 #endif
 }
 
+/* !!FIXME!!
+ * This is a bogus definition to get it to compile.
+ */
+
+struct VIA_PCI_REG_INIT_TABLE {
+	u8 and_val;
+	u8 or_val;
+	u8 bus;
+	u8 dev;
+	u8 func;
+	u8 reg;
+	u8 v1;
+	u8 v2;
+};
+
 /*
  * Added this table 2008-11-28.
  * This table contains the value needed to be set before begin to init DRAM.
diff --git a/src/mainboard/via/epia-m700/driving_clk_phase_data.c b/src/mainboard/via/epia-m700/driving_clk_phase_data.c
index 6309a0717d..0beec20613 100644
--- a/src/mainboard/via/epia-m700/driving_clk_phase_data.c
+++ b/src/mainboard/via/epia-m700/driving_clk_phase_data.c
@@ -204,7 +204,7 @@ static const u8 DDR2_ChA_DQS_Input_Capture_Tbl[DQS_INPUT_CAPTURE_REG_NUM ][DQS_I
 #endif
 
 /* vt6413D */
-static const u8DDR2_ChA_DQS_Input_Capture_Tbl[DQS_INPUT_CAPTURE_REG_NUM][DQS_INPUT_CAPTURE_FREQ_NUM] = {
+static const u8 DDR2_ChA_DQS_Input_Capture_Tbl[DQS_INPUT_CAPTURE_REG_NUM][DQS_INPUT_CAPTURE_FREQ_NUM] = {
 	//    (And NOT) DDR800 DDR667 DDR533 DDR400
 	//Reg  Mask  Value Value Value Value
 	{0x78, 0xC0, 0x0D, 0x07, 0x03, 0x01},	// 1Rank
diff --git a/src/mainboard/via/epia-m700/wakeup.c b/src/mainboard/via/epia-m700/wakeup.c
index b22de15259..011b680b40 100644
--- a/src/mainboard/via/epia-m700/wakeup.c
+++ b/src/mainboard/via/epia-m700/wakeup.c
@@ -131,9 +131,9 @@ void acpi_jump_wake(u32 vector)
 	memcpy((void *)(WAKE_THUNK16_ADDR - 100), jump_to_wakeup,
 	       sizeof(jump_to_wakeup));
 
-	jason_tsc_count();
+	//jason_tsc_count();
 	printk_emerg("file '%s', line %d\n\n", __FILE__, __LINE__);
-	jason_tsc_count_end();
+	//jason_tsc_count_end();
 
 	unsigned long long *real_mode_gdt_entries_at_eseg;
 	real_mode_gdt_entries_at_eseg = WAKE_THUNK16_GDT;		/* Copy from real_mode_gdt_entries and change limition to 1M and data base to 0; */
diff --git a/src/northbridge/via/vx800/dev_init.c b/src/northbridge/via/vx800/dev_init.c
index 390d2a993c..7ec3c86aef 100644
--- a/src/northbridge/via/vx800/dev_init.c
+++ b/src/northbridge/via/vx800/dev_init.c
@@ -298,7 +298,7 @@ Output     : Void
 Purpose   : Set ending address of virtual rank specified by VirRank 
 ===================================================================*/
 
-void SetEndingAddr(DRAM_SYS_ATTR *DramAttr, u8 VirRank,	/* ending address
+void SetEndingAddr(DRAM_SYS_ATTR *DramAttr, u8 VirRank /* ending address
 		   register number indicator (INDEX */, INT8 Value /* (value)
 		   add or subtract value to this and after banks */) {
 	u8 Data;
diff --git a/src/northbridge/via/vx800/dram_util.c b/src/northbridge/via/vx800/dram_util.c
index 35c471fc80..342a6e0454 100644
--- a/src/northbridge/via/vx800/dram_util.c
+++ b/src/northbridge/via/vx800/dram_util.c
@@ -56,11 +56,8 @@ Reference  : None
 
 u32 via_read_phys(volatile u32 addr)
 {
-	volatile u32 *ptr;
 	volatile u32 y;
-//    ptr = (volatile u32 *)addr;
 	y = *(volatile u32 *)addr;
-//    return *ptr;
 	return y;
 }
 
diff --git a/src/northbridge/via/vx800/examples/chipset_init.c b/src/northbridge/via/vx800/examples/chipset_init.c
index 644284eef7..9c00f96939 100644
--- a/src/northbridge/via/vx800/examples/chipset_init.c
+++ b/src/northbridge/via/vx800/examples/chipset_init.c
@@ -24,7 +24,7 @@
 #include <../northbridge/via/vx800/vx800.h>
 
 #include <arch/io.h>
-#include <arch/pci_rawops.h>
+#include "pci_rawops.h"
 
 static const struct VIA_PCI_REG_INIT_TABLE mSbStage1InitTbl[] = {
 	// Combine Stage1 registers
@@ -249,7 +249,7 @@ void AcpiInit(void)
 {
 	device_t_raw rawdevice = 0;
 	u8 sbchiprev;
-	rawdevice = PCI_RAWDEV(0, 0x11, 0);
+	rawdevice = PCI_DEV(0, 0x11, 0);
 	// Set the PMIO base io address 
 	pci_rawmodify_config16(rawdevice, 0x88, VX800_ACPI_IO_BASE,
 			       0xff80);
@@ -277,13 +277,13 @@ void Stage2NbInit(void)
 	device_t_raw rawdevice = 0;
 	u8 nbchiprev;
 	u32 subid = 0;
-	rawdevice = PCI_RAWDEV(0, 0, 4);
+	rawdevice = PCI_DEV(0, 0, 4);
 	nbchiprev = pci_rawread_config8(rawdevice, 0xf6);
 	printk_debug("NB chip revision =%x\n", nbchiprev);
 
 	via_pci_inittable(nbchiprev, mNbStage2InitTable);
 
-	rawdevice = PCI_RAWDEV(0, 0, 0);
+	rawdevice = PCI_DEV(0, 0, 0);
 
 	subid = PCI_DEVICE_ID_VIA_VX855_D0F0 << 16 + PCI_VENDOR_ID_VIA;
 	pci_rawwrite_config32(rawdevice, 0x2C, subid);
@@ -295,15 +295,15 @@ void Stage2NbInit(void)
 
 void IDECSupportOption(u8 sbchiprev)
 {
-	pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, 0, 0x08);
+	pci_rawmodify_config8(PCI_DEV(0, 0x11, 0), 0x50, 0, 0x08);
 
-	pci_rawmodify_config8(PCI_RAWDEV(0, 0xf, 0), 0x45, 0x00, 0x80);
-	pci_rawmodify_config8(PCI_RAWDEV(0, 0xf, 0), 0x0A, 0x01, 0xFF);
-	pci_rawmodify_config8(PCI_RAWDEV(0, 0xf, 0), 0x45, 0x80, 0x00);
-	pci_rawmodify_config8(PCI_RAWDEV(0, 0xf, 0), 0x40, 0x02, 0x00);
+	pci_rawmodify_config8(PCI_DEV(0, 0xf, 0), 0x45, 0x00, 0x80);
+	pci_rawmodify_config8(PCI_DEV(0, 0xf, 0), 0x0A, 0x01, 0xFF);
+	pci_rawmodify_config8(PCI_DEV(0, 0xf, 0), 0x45, 0x80, 0x00);
+	pci_rawmodify_config8(PCI_DEV(0, 0xf, 0), 0x40, 0x02, 0x00);
 
-	pci_rawmodify_config8(PCI_RAWDEV(0, 0xf, 0), 0x09, 0x00, 0x05);	//COMPATIBLE MODE 
-//      pci_rawmodify_config8(PCI_RAWDEV(0, 0xf, 0), 0x09, 0x05, 0x05);//native MODE 
+	pci_rawmodify_config8(PCI_DEV(0, 0xf, 0), 0x09, 0x00, 0x05);	//COMPATIBLE MODE 
+//      pci_rawmodify_config8(PCI_DEV(0, 0xf, 0), 0x09, 0x05, 0x05);//native MODE 
 
 	via_pci_inittable(sbchiprev, IDEC_INIT);
 }
@@ -350,23 +350,23 @@ void InitUHCI(u8 Number, u8 bEnable)
 		Mask = 0x0;
 		Value = 0x1 << BitShift;
 	}
-	pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, Value, Mask);
+	pci_rawmodify_config8(PCI_DEV(0, 0x11, 0), 0x50, Value, Mask);
 
 
 	if (bEnable) {
 		D16 = 0;
-		pci_rawwrite_config16(PCI_RAWDEV(0, 0x10, BaseAddress),
+		pci_rawwrite_config16(PCI_DEV(0, 0x10, BaseAddress),
 				      0x20, D16);
 
 		// Config some Control Register
 		Mask = 0x00;
 		Value = 0x12;
 
-		pci_rawmodify_config8(PCI_RAWDEV(0, 0x10, BaseAddress),
+		pci_rawmodify_config8(PCI_DEV(0, 0x10, BaseAddress),
 				      0x41, Value, Mask);
 		Mask = 0x00;
 		Value = 0xEB;
-		pci_rawmodify_config8(PCI_RAWDEV(0, 0x10, BaseAddress),
+		pci_rawmodify_config8(PCI_DEV(0, 0x10, BaseAddress),
 				      0x4B, Value, Mask);
 	}
 	return;
@@ -407,13 +407,13 @@ void InitEHCI(u8 Number, u8 bEnable)
 		Mask = 0x0;
 		Value = 0x1 << 1;
 	}
-	pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, Value, Mask);
+	pci_rawmodify_config8(PCI_DEV(0, 0x11, 0), 0x50, Value, Mask);
 
 
 	if (bEnable) {
 		// Get Chipset Revision
 		EHCIRevision =
-		    pci_rawread_config8(PCI_RAWDEV(0, 0x10, 4), 0xF6);
+		    pci_rawread_config8(PCI_DEV(0, 0x10, 4), 0xF6);
 		printk_debug("EHCI Revision =%x\n", EHCIRevision);
 		via_pci_inittable(EHCIRevision, mEHCIInitTable);
 	}
@@ -475,9 +475,9 @@ void HpetInit(void)
 {
 	u8 HpetEnable = HPET_ENABLE_BIT;
 	u16 HpetBase = HPET_BASE_ADDRESS;
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), R_SB_HPET_CONTROL,
+	pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), R_SB_HPET_CONTROL,
 			     HpetEnable);
-	pci_rawwrite_config16(PCI_RAWDEV(0, 0x11, 0),
+	pci_rawwrite_config16(PCI_DEV(0, 0x11, 0),
 			      R_SB_HPET_ADDRESS + 1, HpetBase);
 }
 
@@ -512,7 +512,7 @@ void InitPMU(u8 sbchiprev)
 	// Set SCI IRQ and its level trigger
 	Mask = 0x0F;
 	Value = 0x09;
-	pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x82, Value, Mask);
+	pci_rawmodify_config8(PCI_DEV(0, 0x11, 0), 0x82, Value, Mask);
 
 	Mask = 0x02;
 	Value = 0x02;
@@ -533,7 +533,7 @@ void InitCPUCStatueSupport()
 	// Now it is C2 & C4 Up Down Mode
 	Mask = 0xFF;
 	Value = 0x30;
-	pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), R_SB_CX_STATE_BREAK_EVENT_ENABLE_1, Value, Mask);	//SB_LPC_REG
+	pci_rawmodify_config8(PCI_DEV(0, 0x11, 0), R_SB_CX_STATE_BREAK_EVENT_ENABLE_1, Value, Mask);	//SB_LPC_REG
 
 	Mask = 0xFF;
 	Value = 0x1F;
@@ -542,15 +542,15 @@ void InitCPUCStatueSupport()
 
 	Mask = 0x00;
 	Value = 0x80;
-	pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 7), R_SB_PCI_ARBITRATION_2, Value, Mask);	//SB_VLINK_REG
+	pci_rawmodify_config8(PCI_DEV(0, 0x11, 7), R_SB_PCI_ARBITRATION_2, Value, Mask);	//SB_VLINK_REG
 
 	Mask = 0xFF;
 	Value = 0x00;
-	pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), R_SB_MULTI_FUNCTION_SELECT_1, Value, Mask);	//SB_VLINK_REG
+	pci_rawmodify_config8(PCI_DEV(0, 0x11, 0), R_SB_MULTI_FUNCTION_SELECT_1, Value, Mask);	//SB_VLINK_REG
 
 	Mask = 0xFF;
 	Value = 0x1F;
-	pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), R_SB_AUTO_SWITCH_P_STATE, Value, Mask);	//SB_VLINK_REG
+	pci_rawmodify_config8(PCI_DEV(0, 0x11, 0), R_SB_AUTO_SWITCH_P_STATE, Value, Mask);	//SB_VLINK_REG
 }
 
 void InitSBPM(u8 sbchiprev)
@@ -565,7 +565,7 @@ void Stage2SbInit(void)
 	device_t_raw rawdevice = 0;
 	u8 sbchiprev;
 
-	rawdevice = PCI_RAWDEV(0, 11, 0);
+	rawdevice = PCI_DEV(0, 11, 0);
 	sbchiprev = pci_rawread_config8(rawdevice, 0xf6);
 	printk_debug("SB chip revision =%x\n", sbchiprev);
 
@@ -585,7 +585,7 @@ void Stage2SbInit(void)
 
 	HpetInit();
 
-	//pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, 0x76, 0);//SB_VLINK_REG
+	//pci_rawmodify_config8(PCI_DEV(0, 0x11, 0), 0x50, 0x76, 0);//SB_VLINK_REG
 
 }
 
@@ -603,7 +603,7 @@ void init_VIA_chipset(void)
 	Stage2SbInit();
 
 	//5.open hdac
-	pci_rawmodify_config32(PCI_RAWDEV(0, 0x11, 7), 0xd1, 0, 0x04);
+	pci_rawmodify_config32(PCI_DEV(0, 0x11, 7), 0xd1, 0, 0x04);
 	printk_debug("End: init_VIA_chipset\n");
 }
 
@@ -634,27 +634,27 @@ void hardwaremain(int boot_complete)
 
 #if 0
 
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0, 4), 0xa3, 0x80);
-	pci_rawwrite_config8(PCI_RAWDEV(0, 17, 7), 0x60, 0x20);
-	pci_rawwrite_config8(PCI_RAWDEV(0, 17, 7), 0xE5,
-			     pci_rawread_config8(PCI_RAWDEV(0, 3, 0),
+	pci_rawwrite_config8(PCI_DEV(0, 0, 4), 0xa3, 0x80);
+	pci_rawwrite_config8(PCI_DEV(0, 17, 7), 0x60, 0x20);
+	pci_rawwrite_config8(PCI_DEV(0, 17, 7), 0xE5,
+			     pci_rawread_config8(PCI_DEV(0, 3, 0),
 						 0x88));
 #endif
 
-	pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x51, 0x40, 0x40);	//close CE-ATA (Consumer Electronics-ATA) and NFC
+	pci_rawmodify_config8(PCI_DEV(0, 0x11, 0), 0x51, 0x40, 0x40);	//close CE-ATA (Consumer Electronics-ATA) and NFC
 
-	//pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, 0x0, 0x40);//open USB Device Mode Enable 
-	pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, 0x40, 0x40);	//close USB Device Mode
+	//pci_rawmodify_config8(PCI_DEV(0, 0x11, 0), 0x50, 0x0, 0x40);//open USB Device Mode Enable 
+	pci_rawmodify_config8(PCI_DEV(0, 0x11, 0), 0x50, 0x40, 0x40);	//close USB Device Mode
 
-	//pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, 0x04, 0x04);//close USB 1.1 UHCI Port 4-5
-	//pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, 0x02, 0x02);//close USB 2.0 ehci
+	//pci_rawmodify_config8(PCI_DEV(0, 0x11, 0), 0x50, 0x04, 0x04);//close USB 1.1 UHCI Port 4-5
+	//pci_rawmodify_config8(PCI_DEV(0, 0x11, 0), 0x50, 0x02, 0x02);//close USB 2.0 ehci
 
 
-	//pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, 0x00, 0x76);//open all usb and usb mode
-	//pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, 0x76, 0x76);//close all usb
+	//pci_rawmodify_config8(PCI_DEV(0, 0x11, 0), 0x50, 0x00, 0x76);//open all usb and usb mode
+	//pci_rawmodify_config8(PCI_DEV(0, 0x11, 0), 0x50, 0x76, 0x76);//close all usb
 
 	printk_info("=================SB 50h=%02x \n",
-		    pci_rawread_config8(PCI_RAWDEV(0, 0x11, 0), 0x50));
+		    pci_rawread_config8(PCI_DEV(0, 0x11, 0), 0x50));
 
 
 	/* FIXME: Is there a better way to handle this? */
@@ -671,7 +671,7 @@ void hardwaremain(int boot_complete)
 		y = 0;
 		for (; y < 16; y++) {
 			printk_info("%02x ",
-				    pci_rawread_config8(PCI_RAWDEV
+				    pci_rawread_config8(PCI_DEV
 							(0, 0x10, 4),
 							x * 16 + y));
 		}
@@ -690,7 +690,7 @@ void hardwaremain(int boot_complete)
 		y = 0;
 		for (; y < 16; y++) {
 			printk_info("%02x ",
-				    pci_rawread_config8(PCI_RAWDEV
+				    pci_rawread_config8(PCI_DEV
 							(0, 0x10, 4),
 							x * 16 + y));
 		}
@@ -710,7 +710,7 @@ void hardwaremain(int boot_complete)
 		y = 0;
 		for (; y < 16; y++) {
 			printk_info("%02x ",
-				    pci_rawread_config8(PCI_RAWDEV
+				    pci_rawread_config8(PCI_DEV
 							(0, 0x10, 4),
 							x * 16 + y));
 		}
@@ -723,7 +723,7 @@ void hardwaremain(int boot_complete)
 	printk_emerg("file '%s', line %d\n\n", __FILE__, __LINE__);
 
 
-//          pci_rawwrite_config16(PCI_RAWDEV(0, 0xf, 0), 0xBA, 0x0571);
+//          pci_rawwrite_config16(PCI_DEV(0, 0xf, 0), 0xBA, 0x0571);
 
 #if 0
 	x = y = 0;
@@ -732,7 +732,7 @@ void hardwaremain(int boot_complete)
 		y = 0;
 		for (; y < 16; y++) {
 			printk_info("%02x ",
-				    pci_rawread_config8(PCI_RAWDEV
+				    pci_rawread_config8(PCI_DEV
 							(0, 0x10, 4),
 							x * 16 + y));
 		}
@@ -743,10 +743,10 @@ void hardwaremain(int boot_complete)
 
 #if 0
 
-	y = pci_rawread_config8(PCI_RAWDEV(0, 0xf, 0), 0x0d);
+	y = pci_rawread_config8(PCI_DEV(0, 0xf, 0), 0x0d);
 	y &= 0x0f;
 	y |= 0x40;
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0xf, 0), 0x0d, y);
+	pci_rawwrite_config8(PCI_DEV(0, 0xf, 0), 0x0d, y);
 #endif
 
 #if 0
@@ -948,7 +948,7 @@ void hardwaremain(int boot_complete)
 	u8 i;
 /* error form ---- but add the chance to resume
 for(i=0;i<5;i++){
-		pci_rawwrite_config8(PCI_RAWDEV(0, 0, 0), i, d0f0pcitable[i+0xcb]);
+		pci_rawwrite_config8(PCI_DEV(0, 0, 0), i, d0f0pcitable[i+0xcb]);
 	}
 
 	
@@ -956,7 +956,7 @@ for(i=0;i<5;i++){
 
 /* RO reg
 for(i=0;i<5;i++){
-		pci_rawwrite_config8(PCI_RAWDEV(0, 0, 0), i+0xcb, d0f0pcitable[i]);
+		pci_rawwrite_config8(PCI_DEV(0, 0, 0), i+0xcb, d0f0pcitable[i]);
 	}
 */
 
@@ -964,25 +964,25 @@ for(i=0;i<5;i++){
 //boot ok, resume still err in linux    
 #if 1
 	for (i = 0; i < 9; i++) {
-		pci_rawwrite_config8(PCI_RAWDEV(0, 0, 2), i + 0x50,
+		pci_rawwrite_config8(PCI_DEV(0, 0, 2), i + 0x50,
 				     d0f2pcitable[i]);
 	}
 	//9 is warm reset reg,   // boot err in coreboot
 	for (i = 10; i < 64; i++) {
-		pci_rawwrite_config8(PCI_RAWDEV(0, 0, 2), i + 0x50,
+		pci_rawwrite_config8(PCI_DEV(0, 0, 2), i + 0x50,
 				     d0f2pcitable[i]);
 	}
 	//0x90 look d0f2 appendixA1 ,   if set this to 09 or 0b, then some ddr2 will crash.
 	for (i = 65; i < 113; i++) {
-		pci_rawwrite_config8(PCI_RAWDEV(0, 0, 2), i + 0x50,
+		pci_rawwrite_config8(PCI_DEV(0, 0, 2), i + 0x50,
 				     d0f2pcitable[i]);
 	}
 #endif
 #ifdef OPTION_1
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0, 2), 0x66, 0x09);
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0, 2), 0x70, 0xdd);
-	//  pci_rawwrite_config8(PCI_RAWDEV(0, 0, 2), 0x90, 0x09);
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0, 2), 0x92, 0x40);
+	pci_rawwrite_config8(PCI_DEV(0, 0, 2), 0x66, 0x09);
+	pci_rawwrite_config8(PCI_DEV(0, 0, 2), 0x70, 0xdd);
+	//  pci_rawwrite_config8(PCI_DEV(0, 0, 2), 0x90, 0x09);
+	pci_rawwrite_config8(PCI_DEV(0, 0, 2), 0x92, 0x40);
 
 #endif
 
@@ -993,61 +993,61 @@ for(i=0;i<5;i++){
 
 //d0f3 
 /*		*/
-	//      pci_rawwrite_config8(PCI_RAWDEV(0, 0, 3), 0x86, 0x3b);  setting, my lspci is 0x29
+	//      pci_rawwrite_config8(PCI_DEV(0, 0, 3), 0x86, 0x3b);  setting, my lspci is 0x29
 	//set bit4 cause the ide not be found
-//              pci_rawwrite_config8(PCI_RAWDEV(0, 0, 3), 0x86, 0x2b);
+//              pci_rawwrite_config8(PCI_DEV(0, 0, 3), 0x86, 0x2b);
 	//set bit1 cause the ide not be found
 
-//              pci_rawwrite_config8(PCI_RAWDEV(0, 0, 3), 0x86, 0x29);
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0, 3), 0x95, 0x05);
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0, 3), 0x99, 0x12);
+//              pci_rawwrite_config8(PCI_DEV(0, 0, 3), 0x86, 0x29);
+	pci_rawwrite_config8(PCI_DEV(0, 0, 3), 0x95, 0x05);
+	pci_rawwrite_config8(PCI_DEV(0, 0, 3), 0x99, 0x12);
 
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0, 3), 0xde, 0x00);
+	pci_rawwrite_config8(PCI_DEV(0, 0, 3), 0xde, 0x00);
 #endif
 
 //boot ok,  resume err in coreboot 
 #if 1
 	for (i = 0; i < 99; i++) {
-		pci_rawwrite_config8(PCI_RAWDEV(0, 0, 4), i + 0x8d,
+		pci_rawwrite_config8(PCI_DEV(0, 0, 4), i + 0x8d,
 				     d0f4pcitable[i]);
 	}
 #endif
 
 #ifdef OPTION_1
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0, 4), 0xe9, 0x90);
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0, 4), 0xec, 0x0);
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0, 4), 0xed, 0x0);
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0, 4), 0xee, 0x0);
+	pci_rawwrite_config8(PCI_DEV(0, 0, 4), 0xe9, 0x90);
+	pci_rawwrite_config8(PCI_DEV(0, 0, 4), 0xec, 0x0);
+	pci_rawwrite_config8(PCI_DEV(0, 0, 4), 0xed, 0x0);
+	pci_rawwrite_config8(PCI_DEV(0, 0, 4), 0xee, 0x0);
 #endif
 
 
 #if 1
 //boot ok, resume still err in linux    
 	for (i = 0; i < 160; i++) {
-		pci_rawwrite_config8(PCI_RAWDEV(0, 0, 5), i + 0x60,
+		pci_rawwrite_config8(PCI_DEV(0, 0, 5), i + 0x60,
 				     d0f5pcitable[i]);
 	}
 	for (i = 0; i < 144; i++) {
-		pci_rawwrite_config8(PCI_RAWDEV(0, 0, 7), i + 0x60,
+		pci_rawwrite_config8(PCI_DEV(0, 0, 7), i + 0x60,
 				     d0f7pcitable[i]);
 	}
 	for (i = 0; i < 3; i++) {
-		pci_rawwrite_config8(PCI_RAWDEV(0, 1, 0), i + 0xb0,
+		pci_rawwrite_config8(PCI_DEV(0, 1, 0), i + 0xb0,
 				     d1f0pcitable[i]);
 	}
 	for (i = 0; i < 96; i++) {
-		pci_rawwrite_config8(PCI_RAWDEV(0, 0xc, 0), i + 0x40,
+		pci_rawwrite_config8(PCI_DEV(0, 0xc, 0), i + 0x40,
 				     dcf0pcitable[i]);
 	}
 #endif
 
 #ifdef OPTION_1
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0, 7), 0x61, 0x0);
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0, 7), 0x63, 0x0);
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0, 7), 0x76, 0xd0);
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0xc, 0), 0x88, 0x81);
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0xc, 0), 0x89, 0x01);
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0xc, 0), 0x8A, 0x60);
+	pci_rawwrite_config8(PCI_DEV(0, 0, 7), 0x61, 0x0);
+	pci_rawwrite_config8(PCI_DEV(0, 0, 7), 0x63, 0x0);
+	pci_rawwrite_config8(PCI_DEV(0, 0, 7), 0x76, 0xd0);
+	pci_rawwrite_config8(PCI_DEV(0, 0xc, 0), 0x88, 0x81);
+	pci_rawwrite_config8(PCI_DEV(0, 0xc, 0), 0x89, 0x01);
+	pci_rawwrite_config8(PCI_DEV(0, 0xc, 0), 0x8A, 0x60);
 #endif
 
 //d15f0
@@ -1057,24 +1057,24 @@ for(i=0;i<5;i++){
 
 #if 1
 
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0x10, 0), 0x4a, 0xa2);	// no affect.
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0x10, 1), 0x4a, 0xa2);
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0x10, 2), 0x4a, 0xa2);
+	pci_rawwrite_config8(PCI_DEV(0, 0x10, 0), 0x4a, 0xa2);	// no affect.
+	pci_rawwrite_config8(PCI_DEV(0, 0x10, 1), 0x4a, 0xa2);
+	pci_rawwrite_config8(PCI_DEV(0, 0x10, 2), 0x4a, 0xa2);
 
 //boot ok, resume still err in linux,  and if disable USB, then all ok
 //      for(i=0;i<48;i++){
 	for (i = 0; i < 44; i++) {
-		pci_rawwrite_config8(PCI_RAWDEV(0, 0x10, 4), i + 0x40,
+		pci_rawwrite_config8(PCI_DEV(0, 0x10, 4), i + 0x40,
 				     d10f4pcitable[i]);
 	}
 #endif
 
 //#ifdef NOOPTION_1
 #if 0
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0x10, 4), 0x6b, 0x01);
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0x10, 4), 0x6d, 0x00);
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0x10, 4), 0x6e, 0x08);
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0x10, 4), 0x6f, 0x80);
+	pci_rawwrite_config8(PCI_DEV(0, 0x10, 4), 0x6b, 0x01);
+	pci_rawwrite_config8(PCI_DEV(0, 0x10, 4), 0x6d, 0x00);
+	pci_rawwrite_config8(PCI_DEV(0, 0x10, 4), 0x6e, 0x08);
+	pci_rawwrite_config8(PCI_DEV(0, 0x10, 4), 0x6f, 0x80);
 #endif
 
 
@@ -1083,171 +1083,171 @@ for(i=0;i<5;i++){
 //before (11.0)is add, s3 resume has already always dead in first resume(more frequenly), and sleep ok
 //      for(i=0;i<192;i++){
 	for (i = 0; i < 6; i++) {
-		pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40,
+		pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), i + 0x40,
 				     d11f0pcitable[i]);
 	}
 	//6 is uart and dvp vcp,   will have // HAVE no com1 ,and no gui show,textmode ok ,s3 sleep ok, resume fail
 
 	//7-18 is my familar part
 	for (i = 7; i < 18; i++) {	//sleep ok ,resume sleep err 2 
-		pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40,
+		pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), i + 0x40,
 				     d11f0pcitable[i]);
 	}
 
 
 	for (i = 18; i < 21; i++) {	//sleep ok ,   sleep err 1, resume 
-		pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40,
+		pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), i + 0x40,
 				     d11f0pcitable[i]);
 	}
 	//0x55 56 57 irq intA#B#C# linkA#linkB#linkC#
 	for (i = 24; i < 27; i++) {	//sleep ok , resume sleep err 1  resume  1
-		pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40,
+		pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), i + 0x40,
 				     d11f0pcitable[i]);
 	}
 	//5b port 80h
-	pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x5b, 0x0, 0x08);
+	pci_rawmodify_config8(PCI_DEV(0, 0x11, 0), 0x5b, 0x0, 0x08);
 	//          i++;
-	//      pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i+0x40, d11f0pcitable[i]);
+	//      pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), i+0x40, d11f0pcitable[i]);
 
 	for (i = 28; i < 72; i++) {	//sleep ok , resume  sleep err 1 , resume 1ci
-		pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40,
+		pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), i + 0x40,
 				     d11f0pcitable[i]);
 	}
 	//7273ACPI BASE
 
 	for (i = 74; i < 112; i++) {	//boot ok, resume still err in linux
-		pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40,
+		pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), i + 0x40,
 				     d11f0pcitable[i]);
 	}
 
 	//B0B4B5 dvp vcp,  if copy this ,then no uart, no gui(of unbuntu)
-	// pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), 0xb0, d11f0pcitable[112]);
-	i = pci_rawread_config8(PCI_RAWDEV(0, 17, 0), 0xB0);
+	// pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), 0xb0, d11f0pcitable[112]);
+	i = pci_rawread_config8(PCI_DEV(0, 17, 0), 0xB0);
 	//multiplex with VCP
 	//    i = i | 0x30;
 	i = i & 0xf7;
-	pci_rawwrite_config8(PCI_RAWDEV(0, 17, 0), 0xB0, i);
+	pci_rawwrite_config8(PCI_DEV(0, 17, 0), 0xB0, i);
 
 
 
 	for (i = 113; i < 114; i++) {	//boot ok, resume still err in linux
-		pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40,
+		pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), i + 0x40,
 				     d11f0pcitable[i]);
 	}
 
 	for (i = 115; i < 116; i++) {	//boot ok, resume still err in linux
-		pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40,
+		pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), i + 0x40,
 				     d11f0pcitable[i]);
 	}
 
 
 	for (i = 118; i < 192; i++) {	//boot ok, resume still err in linux
-		pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40,
+		pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), i + 0x40,
 				     d11f0pcitable[i]);
 	}
 #endif
 #ifdef NOOPTION_1
 //      for(i=0;i<192;i++){
 	for (i = 0; i < 6; i++) {
-		pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40,
+		pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), i + 0x40,
 				     OPTION_1_d11f0pcitable[i]);
 	}
 	//6 is uart and dvp vcp,   will have // HAVE no com1 ,and no gui show,textmode ok ,s3 sleep ok, resume fail
 
 	//7-18 is my familar part
 	for (i = 7; i < 18; i++) {	//   sleep err 2
-		pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40,
+		pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), i + 0x40,
 				     OPTION_1_d11f0pcitable[i]);
 	}
 
 	for (i = 18; i < 21; i++) {	//sleep ok , resume ???
-		pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40,
+		pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), i + 0x40,
 				     d11f0pcitable[i]);
 	}
 	//0x55 56 57 irq intA#B#C# linkA#linkB#linkC#
 	for (i = 24; i < 27; i++) {	//sleep ok , resume ???
-		pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40,
+		pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), i + 0x40,
 				     d11f0pcitable[i]);
 	}
 	//5b port 80h
 	i++;
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40,
+	pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), i + 0x40,
 			     OPTION_1_d11f0pcitable[i]);
 
 	for (i = 28; i < 72; i++) {	//sleep ok , resume???
-		pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40,
+		pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), i + 0x40,
 				     OPTION_1_d11f0pcitable[i]);
 	}
 	//7273ACPI BASE
 
 	for (i = 74; i < 112; i++) {	//boot ok, resume still err in linux
-		pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40,
+		pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), i + 0x40,
 				     OPTION_1_d11f0pcitable[i]);
 	}
 
 	//B0B4B5 dvp vcp,  if copy this ,then no uart, no gui(of unbuntu)
-	// pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), 0xb0, OPTION_1_d11f0pcitable[112]);
-	i = pci_rawread_config8(PCI_RAWDEV(0, 17, 0), 0xB0);
+	// pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), 0xb0, OPTION_1_d11f0pcitable[112]);
+	i = pci_rawread_config8(PCI_DEV(0, 17, 0), 0xB0);
 	//multiplex with VCP
 	//    i = i | 0x30;
 	i = i & 0xf7;
-	pci_rawwrite_config8(PCI_RAWDEV(0, 17, 0), 0xB0, i);
+	pci_rawwrite_config8(PCI_DEV(0, 17, 0), 0xB0, i);
 
 
 
 	for (i = 113; i < 114; i++) {	//boot ok, resume still err in linux
-		pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40,
+		pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), i + 0x40,
 				     OPTION_1_d11f0pcitable[i]);
 	}
 
 	for (i = 115; i < 116; i++) {	//boot ok, resume still err in linux
-		pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40,
+		pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), i + 0x40,
 				     OPTION_1_d11f0pcitable[i]);
 	}
 
 	for (i = 118; i < 192; i++) {	//boot ok, resume still err in linux
-		pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40,
+		pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), i + 0x40,
 				     OPTION_1_d11f0pcitable[i]);
 	}
 #endif
 
 #if 1
-	pci_rawwrite_config16(PCI_RAWDEV(0, 0xf, 0), 0xBA, PCI_DEVICE_ID_VIA_VX855_IDE);	//5324
-	pci_rawwrite_config16(PCI_RAWDEV(0, 0xf, 0), 0xBE,
+	pci_rawwrite_config16(PCI_DEV(0, 0xf, 0), 0xBA, PCI_DEVICE_ID_VIA_VX855_IDE);	//5324
+	pci_rawwrite_config16(PCI_DEV(0, 0xf, 0), 0xBE,
 			      PCI_DEVICE_ID_VIA_VX855_IDE);
-	pci_rawwrite_config16(PCI_RAWDEV(0, 0x11, 0), 0xA0,
+	pci_rawwrite_config16(PCI_DEV(0, 0x11, 0), 0xA0,
 			      PCI_VENDOR_ID_VIA);
-	pci_rawwrite_config16(PCI_RAWDEV(0, 0x11, 0), 0xA2, PCI_DEVICE_ID_VIA_VX855_LPC);	//8353
-	i = pci_rawread_config8(PCI_RAWDEV(0, 0x11, 0), 0x79);
+	pci_rawwrite_config16(PCI_DEV(0, 0x11, 0), 0xA2, PCI_DEVICE_ID_VIA_VX855_LPC);	//8353
+	i = pci_rawread_config8(PCI_DEV(0, 0x11, 0), 0x79);
 	i &= ~0x40;
 	i |= 0x40;
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), 0x79, i);
-	pci_rawwrite_config16(PCI_RAWDEV(0, 0x11, 0), 0x72,
+	pci_rawwrite_config8(PCI_DEV(0, 0x11, 0), 0x79, i);
+	pci_rawwrite_config16(PCI_DEV(0, 0x11, 0), 0x72,
 			      PCI_DEVICE_ID_VIA_VX855_LPC);
 
 
 //boot ok, resume still err in linux
 	for (i = 0; i < 192; i++) {
-		pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 7), i + 0x40,
+		pci_rawwrite_config8(PCI_DEV(0, 0x11, 7), i + 0x40,
 				     d11f7pcitable[i]);
 	}
 #endif
 #ifdef OPTION_1
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 7), 0x61, 0x2a);
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 7), 0x63, 0xa0);
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 7), 0x64, 0xaa);
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 7), 0x84, 0x0);
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 7), 0x88, 0x02);
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 7), 0xe6, 0x3f);
+	pci_rawwrite_config8(PCI_DEV(0, 0x11, 7), 0x61, 0x2a);
+	pci_rawwrite_config8(PCI_DEV(0, 0x11, 7), 0x63, 0xa0);
+	pci_rawwrite_config8(PCI_DEV(0, 0x11, 7), 0x64, 0xaa);
+	pci_rawwrite_config8(PCI_DEV(0, 0x11, 7), 0x84, 0x0);
+	pci_rawwrite_config8(PCI_DEV(0, 0x11, 7), 0x88, 0x02);
+	pci_rawwrite_config8(PCI_DEV(0, 0x11, 7), 0xe6, 0x3f);
 #endif
 
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0x14, 0), 0x40, 0x20);
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0x14, 0), 0x41, 0x31);
+	pci_rawwrite_config8(PCI_DEV(0, 0x14, 0), 0x40, 0x20);
+	pci_rawwrite_config8(PCI_DEV(0, 0x14, 0), 0x41, 0x31);
 
 
 
 #ifdef OPTION_1
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0x14, 0), 0x40, 0x00);
+	pci_rawwrite_config8(PCI_DEV(0, 0x14, 0), 0x40, 0x00);
 #endif
 
 
@@ -1256,11 +1256,11 @@ for(i=0;i<5;i++){
 	u8 i911;
 	//disable CHB L.L
 	//set VGA memory selection
-	i911 = pci_rawread_config8(PCI_RAWDEV(0, 0x1, 0), 0xb0);
+	i911 = pci_rawread_config8(PCI_DEV(0, 0x1, 0), 0xb0);
 	i911 &= 0xF8;
 	//ByteVal |= 0x03;
 	i911 |= 0x01;
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0x1, 0), 0xb0, i911);
+	pci_rawwrite_config8(PCI_DEV(0, 0x1, 0), 0xb0, i911);
 
 
 #if 1
@@ -1290,8 +1290,8 @@ for(i=0;i<5;i++){
 
 
 
-	//pci_rawmodify_config8(PCI_RAWDEV(0, 0x10, 4), 0x04, 0x17, 0x17);//
-//      pci_rawmodify_config8(PCI_RAWDEV(0, 0x10, 4), 0x0c, 0x08, 0xff);///
+	//pci_rawmodify_config8(PCI_DEV(0, 0x10, 4), 0x04, 0x17, 0x17);//
+//      pci_rawmodify_config8(PCI_DEV(0, 0x10, 4), 0x0c, 0x08, 0xff);///
 
 
 
diff --git a/src/northbridge/via/vx800/northbridge.c b/src/northbridge/via/vx800/northbridge.c
index 7042f67f12..d1f60635bb 100644
--- a/src/northbridge/via/vx800/northbridge.c
+++ b/src/northbridge/via/vx800/northbridge.c
@@ -35,6 +35,11 @@
 #include "northbridge.h"
 #include "vx800.h"
 
+/* !!FIXME!!  This was meant to be a CONFIG option */
+#define VIACONFIG_TOP_SM_SIZE_MB 32	// Set frame buffer 32M for default
+/* !!FIXME!!  I declared this to fix the build. */
+u8 acpi_sleep_type = 0;
+
 static void memctrl_init(device_t dev)
 {
 /*
diff --git a/src/northbridge/via/vx800/raminit.c b/src/northbridge/via/vx800/raminit.c
index bf1eed92e9..ae9777e42c 100644
--- a/src/northbridge/via/vx800/raminit.c
+++ b/src/northbridge/via/vx800/raminit.c
@@ -20,7 +20,6 @@
 #include <spd.h>
 #include <sdram_mode.h>
 #include <delay.h>
-#include <arch/pci_rawops.h>
 
 #define DEBUG_RAM_SETUP 1
 
diff --git a/src/northbridge/via/vx800/uma_ram_setting.c b/src/northbridge/via/vx800/uma_ram_setting.c
index e670a940ec..91329e21ea 100644
--- a/src/northbridge/via/vx800/uma_ram_setting.c
+++ b/src/northbridge/via/vx800/uma_ram_setting.c
@@ -17,6 +17,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
+#include "pci_rawops.h"
+
 typedef struct __UMA_RAM_tag {
 	u16 DramSize;
 	u8 D0F3Val;
@@ -48,6 +50,9 @@ typedef struct __UMA_RAM_tag {
 #define VGA_PORT_32M	0xF0
 #define VGA_PORT_16M	0xF8
 
+#define VIACONFIG_VGA_PCI_10 0xf8000008
+#define VIACONFIG_VGA_PCI_14 0xfc000000
+
 static const UMARAM UMARamArr[] = {
 	{0, UMARAM_0M, FB_4M, 0xFE},
 	{8, UMARAM_8M, FB_8M, 0xFC},
@@ -168,10 +173,10 @@ void SetUMARam(void)
 	pci_write_config32(vga_dev, 0x14, Tmp);
 
 //enable direct cpu frame buffer access
-	i = pci_rawread_config8(PCI_RAWDEV(0, 0, 3), 0xa1);
+	i = pci_conf1_read8(PCI_DEV(0, 0, 3), 0xa1);
 	i = (i & 0xf0) | (VIACONFIG_VGA_PCI_10 >> 28);
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0, 3), 0xa1, i);
-	pci_rawwrite_config8(PCI_RAWDEV(0, 0, 3), 0xa0, 0x01);
+	pci_conf1_write8(PCI_DEV(0, 0, 3), 0xa1, i);
+	pci_conf1_write8(PCI_DEV(0, 0, 3), 0xa0, 0x01);
 
 	//enable GFx memory space access control for S.L and mmio
 	ByteVal = pci_read_config8(d0f0_dev, 0xD4);
diff --git a/src/northbridge/via/vx800/vga.c b/src/northbridge/via/vx800/vga.c
index b29f12ae49..a3bf81bd08 100644
--- a/src/northbridge/via/vx800/vga.c
+++ b/src/northbridge/via/vx800/vga.c
@@ -45,19 +45,22 @@
 #define CRTC_INDEX	0x3d4
 #define CRTC_DATA	0x3d5
 
+/* !!FIXME!! These were CONFIG_ options.  Fix it in uma_ram_setting.c too. */
+#define VIACONFIG_VGA_PCI_10 0xf8000008
+#define VIACONFIG_VGA_PCI_14 0xfc000000
+
 void write_protect_vgabios(void)
 {
 	device_t dev;
 
 	printk_info("write_protect_vgabios\n");
 	/* there are two possible devices. Just do both. */
-	dev =
-	    dev_find_device(PCI_VENDOR_ID_VIA,
-			    PCI_DEVICE_ID_VIA_VX855_MEMCTRL, 0);
+	dev = dev_find_device(PCI_VENDOR_ID_VIA,
+			      PCI_DEVICE_ID_VIA_VX855_MEMCTRL, 0);
 	if (dev)
 		pci_write_config8(dev, 0x80, 0xff);
 	/*vx855 no th 0x61 reg */
-	/*dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX855_NB_VLINK, 0);
+	/*dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX855_VLINK, 0);
 	   //if(dev)
 	   //   pci_write_config8(dev, 0x61, 0xff); */
 }
@@ -90,7 +93,7 @@ static void vga_init(device_t dev)
 	printk_debug("DO THE VGA BIOS\n");
 
 	do_vgabios();
-	if ((acpi_sleep_type == 3) || (PAYLOAD_IS_SEABIOS == 0)) {
+	if ((acpi_sleep_type == 3)/* || (PAYLOAD_IS_SEABIOS == 0)*/) {
 		printk_debug("Enable VGA console\n");
 		// remove this function since in cn700 it is said "VGA seems to work without this, but crash & burn with it"
 		//but the existense of  vga_enable_console()  seems do not hurt my coreboot. XP+ubuntu s3 can resume with and without this function.
@@ -103,7 +106,7 @@ static void vga_init(device_t dev)
 	pci_rom_load(dev, 0xfff80000);
 	run_bios(dev, 0xc0000);
 #endif
-	if ((acpi_sleep_type == 3) || (PAYLOAD_IS_SEABIOS == 0)) {
+	if ((acpi_sleep_type == 3)/* || (PAYLOAD_IS_SEABIOS == 0)*/) {
 		/* It's not clear if these need to be programmed before or after
 		 * the VGA bios runs. Try both, clean up later */
 		/* Set memory rate to 200MHz */
@@ -125,7 +128,7 @@ static void vga_init(device_t dev)
 
 static void vga_read_resources(device_t dev)
 {
-	dev->rom_address = (void *)(0xffffffff - FULL_ROM_SIZE + 1);
+	dev->rom_address = (void *)(0xffffffff - CONFIG_ROM_SIZE + 1);
 	dev->on_mainboard = 1;
 	pci_dev_read_resources(dev);
 }
diff --git a/src/northbridge/via/vx800/vgabios.c b/src/northbridge/via/vx800/vgabios.c
index 34d3bce939..a2010ba1d5 100644
--- a/src/northbridge/via/vx800/vgabios.c
+++ b/src/northbridge/via/vx800/vgabios.c
@@ -118,7 +118,7 @@ extern u8 acpi_sleep_type;
 
 static void real_mode_switch_call_vga(unsigned long devfn)
 {
-	if ((acpi_sleep_type == 0) && (PAYLOAD_IS_SEABIOS == 1))
+	if ((acpi_sleep_type == 0)/* && (PAYLOAD_IS_SEABIOS == 1)*/)
 		return;
 	__asm__ __volatile__(
 				    // paranoia -- does ecx get saved? not sure. This is 
@@ -205,7 +205,7 @@ extern char real_mode_switch_end[];
    epia-m does not always autosence the main console so forcing it on is good !! */
 void vga_enable_console()
 {
-	if ((acpi_sleep_type == 0) && (PAYLOAD_IS_SEABIOS == 1))
+	if ((acpi_sleep_type == 0)/* && (PAYLOAD_IS_SEABIOS == 1)*/)
 		return;
 	__asm__ __volatile__(
 				    /* paranoia -- does ecx get saved? not sure. This is 
@@ -319,7 +319,7 @@ void do_vgabios(void)
 	/* declare rom address here - keep any config data out of the way
 	 * of core LXB stuff */
 
-	rom = 0xffffffff - FULL_ROM_SIZE + 1;
+	rom = 0xffffffff - CONFIG_ROM_SIZE + 1;
 	pci_write_config32(dev, PCI_ROM_ADDRESS, rom | 1);
 	printk_debug("rom base: %x\n", rom);
 	buf = (unsigned char *)rom;
@@ -522,7 +522,9 @@ int biosint(unsigned long intnumber,
 
 	// cases in a good compiler are just as good as your own tables. 
 	switch (intnumber) {
-	case 0...15:
+	case 0: case 1: case 2: case 3: case 4: case 5:
+	case 6: case 7: case 8: case 9: case 10:
+	case 11: case 12: case 13: case 14: case 15:
 		// These are not BIOS service, but the CPU-generated exceptions
 		printk_info("biosint: Oops, exception %u\n", intnumber);
 		if (esp < 0x1000) {
@@ -535,7 +537,7 @@ int biosint(unsigned long intnumber,
 		}
 		printk_debug("biosint: Bailing out\n");
 		// "longjmp"
-		if ((acpi_sleep_type == 3) || (PAYLOAD_IS_SEABIOS == 0))	// add this to keep same with kevin's seabios patch in 2008-9-8
+		if ((acpi_sleep_type == 3)/* || (PAYLOAD_IS_SEABIOS == 0)*/)	// add this to keep same with kevin's seabios patch in 2008-9-8
 			vga_exit();
 		break;
 
diff --git a/src/northbridge/via/vx800/vx800.h b/src/northbridge/via/vx800/vx800.h
index f77fd95b19..f23974342e 100644
--- a/src/northbridge/via/vx800/vx800.h
+++ b/src/northbridge/via/vx800/vx800.h
@@ -25,12 +25,12 @@ static void vx800_noop()
 {
 }
 #endif
-#define REV_B0  0x10
+//#define REV_B0 0x10
 #define REV_B1 0x11
-#define REV_B2 0x12
+//#define REV_B2 0x12
 #define REV_B3 0x13
 #define REV_B4 0x14
-#define REV_B2 0xB4
+//#define REV_B2 0xB4
 #define REV_B0 0x00
 #define REV_B2 0x01
 
diff --git a/src/northbridge/via/vx800/vx800_early_smbus.c b/src/northbridge/via/vx800/vx800_early_smbus.c
index 247eab91fd..6fda8b0e0a 100644
--- a/src/northbridge/via/vx800/vx800_early_smbus.c
+++ b/src/northbridge/via/vx800/vx800_early_smbus.c
@@ -114,7 +114,6 @@ static void smbus_reset(void)
 /* Public functions */
 static unsigned int set_ics_data(unsigned char dev, int data, char len)
 {
-	int i;
 	smbus_reset();
 	/* clear host data port */
 	outb(0x00, SMBHSTDAT0);
@@ -125,7 +124,7 @@ static unsigned int set_ics_data(unsigned char dev, int data, char len)
 	inb(SMBHSTCTL);
 
 	/* fill blocktransfer array */
-	if (dev = 0xd2) {
+	if (dev == 0xd2) {
 		//char d2_data[] = {0x0d,0x00,0x3f,0xcd,0x7f,0xbf,0x1a,0x2a,0x01,0x0f,0x0b,0x00,0x8d,0x9b};
 		outb(0x0d, SMBBLKDAT);
 		outb(0x00, SMBBLKDAT);