diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2013-10-04 11:15:48 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@google.com> | 2014-02-05 05:24:13 +0100 |
| commit | c0270aa6d0e183ceb04566b6e9e3939bd9215d35 (patch) | |
| tree | d81de8427f9153e1c2744c8cd09f6be115c59e5e | |
| parent | fd039f7f4d84b1c04dba81874068f8ea94620f87 (diff) | |
| download | coreboot-c0270aa6d0e183ceb04566b6e9e3939bd9215d35.tar.xz | |
baytrail: load microcode in bootblock
Start loading microcode in the bootblock. This way
no caching has been set up and cache-as-ram mode
will be running in a validated configruation (with ucode
patch).
BUG=chrome-os-partner:22858
BRANCH=None
TEST=Built and booted. Confirmed microcode is loaded.
Change-Id: I6fd1d8e55bcc9d799b11d9faed771ac50dc120a2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/171861
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4863
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
| -rw-r--r-- | src/soc/intel/baytrail/bootblock/bootblock.c | 15 |
1 files changed, 12 insertions, 3 deletions
diff --git a/src/soc/intel/baytrail/bootblock/bootblock.c b/src/soc/intel/baytrail/bootblock/bootblock.c index 70ccc21f8b..fa0d9eee8d 100644 --- a/src/soc/intel/baytrail/bootblock/bootblock.c +++ b/src/soc/intel/baytrail/bootblock/bootblock.c @@ -22,6 +22,7 @@ #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <baytrail/iosf.h> +#include <cpu/intel/microcode/microcode.c> static void set_var_mtrr(int reg, uint32_t base, uint32_t size, int type) { @@ -49,12 +50,10 @@ static void enable_rom_caching(void) wrmsr(MTRRdefType_MSR, msr); } -static void bootblock_cpu_init(void) +static void setup_mmconfig(void) { uint32_t reg; - enable_rom_caching(); - /* Set up the MMCONF range. The register lives in the BUNIT. The * IO variant of the config access needs to be used initially to * properly configure as the IOSF access registers live in PCI @@ -68,3 +67,13 @@ static void bootblock_cpu_init(void) IOSF_REG(BUNIT_MMCONF_REG) | IOSF_BYTE_EN; pci_io_write_config32(IOSF_PCI_DEV, MCR_REG, reg); } + +static void bootblock_cpu_init(void) +{ + /* Allow memory-mapped PCI config access. */ + setup_mmconfig(); + + /* Load microcode before any caching. */ + intel_update_microcode_from_cbfs(); + enable_rom_caching(); +} |