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authorFurquan Shaikh <furquan@chromium.org>2017-08-25 09:50:15 -0700
committerFurquan Shaikh <furquan@google.com>2017-08-28 01:19:36 +0000
commitc3e4f6344dfec53c0ac5a07632270816a30046b9 (patch)
treefc7272dbbb00b5c184e0fc0e31e1ef98e490e083
parent5bb27b7815b00ed789f474133eb52c73075a200f (diff)
downloadcoreboot-c3e4f6344dfec53c0ac5a07632270816a30046b9.tar.xz
mainboard/google/poppy: Tune I2C params (hcnt, lcnt, hold time)
Tune I2C params for I2C buses 0, 1, 2, 4 and 5 to ensure that the frequency does not exceed 400KHz. BUG=b:35948024 TEST=Verified for 25 iterations that the frequency on each bus ranges <= 400KHz. I2C0: 375 - 400 I2C1: 377 - 400 I2C2: 377 - 400 I2C4: 375 - 397 I2C5: 375 - 397 Change-Id: Ie30e1a12b66c4660b648a585c4dfd66faf004129 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/21208 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/mainboard/google/poppy/variants/baseboard/devicetree.cb77
1 files changed, 65 insertions, 12 deletions
diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
index 2324557320..6aba677ea2 100644
--- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
@@ -165,12 +165,71 @@ chip soc/intel/skylake
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port
register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty
- register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" # Touchscreen
- register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3" # H1
- register "i2c_voltage[2]" = "I2C_VOLTAGE_1V8" # Camera
- register "i2c_voltage[3]" = "I2C_VOLTAGE_1V8" # Pen
- register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # Camera
- register "i2c_voltage[5]" = "I2C_VOLTAGE_1V8" # Audio
+ # Touchscreen
+ register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3"
+ register "i2c[0]" = "{
+ .speed = I2C_SPEED_FAST,
+ .speed_config[0] = {
+ .speed = I2C_SPEED_FAST,
+ .scl_lcnt = 185,
+ .scl_hcnt = 90,
+ .sda_hold = 36,
+ },
+ }"
+
+ # H1
+ register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3"
+ register "i2c[1]" = "{
+ .speed = I2C_SPEED_FAST,
+ .speed_config[0] = {
+ .speed = I2C_SPEED_FAST,
+ .scl_lcnt = 190,
+ .scl_hcnt = 100,
+ .sda_hold = 36,
+ },
+ .early_init = 1,
+ }"
+
+
+ # Camera
+ register "i2c_voltage[2]" = "I2C_VOLTAGE_1V8"
+ register "i2c[2]" = "{
+ .speed = I2C_SPEED_FAST,
+ .speed_config[0] = {
+ .speed = I2C_SPEED_FAST,
+ .scl_lcnt = 190,
+ .scl_hcnt = 97,
+ .sda_hold = 36,
+ },
+ }"
+
+ # Pen
+ register "i2c_voltage[3]" = "I2C_VOLTAGE_1V8"
+
+ # Camera
+ register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8"
+ register "i2c[4]" = "{
+ .speed = I2C_SPEED_FAST,
+ .speed_config[0] = {
+ .speed = I2C_SPEED_FAST,
+ .scl_lcnt = 190,
+ .scl_hcnt = 97,
+ .sda_hold = 36,
+ },
+ }"
+
+ # Audio
+ register "i2c_voltage[5]" = "I2C_VOLTAGE_1V8"
+ register "i2c[5]" = "{
+ .speed = I2C_SPEED_FAST,
+ .speed_config[0] = {
+ .speed = I2C_SPEED_FAST,
+ .scl_lcnt = 190,
+ .scl_hcnt = 98,
+ .sda_hold = 36,
+ },
+ }"
+
# Use GSPI0 for cr50 TPM. Early init is required to set up a BAR for TPM
# communication before memory is up.
@@ -179,12 +238,6 @@ chip soc/intel/skylake
.early_init = 1,
}"
- # Configure I2C1 for cr50 TPM. Early init is required to set up a BAR
- # for TPM communication before memory is up.
- register "i2c[1]" = "{
- .early_init = 1,
- }"
-
# Must leave UART0 enabled or SD/eMMC will not work as PCI
register "SerialIoDevMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,