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authorPatrick Georgi <pgeorgi@chromium.org>2015-07-27 23:18:15 +0200
committerPatrick Georgi <pgeorgi@google.com>2015-07-29 19:25:14 +0200
commitc3f72751f8c692f9c763aadf22409937c938f426 (patch)
tree3753cb44f2304f7c3e6d3e1facad333b1c30c539
parent5e0a2e2d33433b564d121a20e5ab7726c74713ec (diff)
downloadcoreboot-c3f72751f8c692f9c763aadf22409937c938f426.tar.xz
google/parrot: Implement functions required by CHROMEOS
BRANCH=none BUG=chromium:513990 TEST=google/parrot builds Change-Id: I5e354d6160e554f1c41e84eac6102e84de34b81d Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: d5a6253e6f19815736a6b433f6c58e3be2e5841b Original-Change-Id: I3a3bf9ead333d56472f856c9efefff239fb70586 Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/288852 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/11063 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
-rw-r--r--src/mainboard/google/parrot/chromeos.c41
1 files changed, 36 insertions, 5 deletions
diff --git a/src/mainboard/google/parrot/chromeos.c b/src/mainboard/google/parrot/chromeos.c
index 0c7f45adde..164e192188 100644
--- a/src/mainboard/google/parrot/chromeos.c
+++ b/src/mainboard/google/parrot/chromeos.c
@@ -43,16 +43,13 @@ void fill_lb_gpios(struct lb_gpios *gpios)
if (!gpio_base)
return;
- u32 gp_lvl = inl(gpio_base + GP_LVL);
- u32 gp_lvl3 = inl(gpio_base + GP_LVL3);
-
gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio));
gpios->count = GPIO_COUNT;
/* Write Protect: GPIO70 active high */
gpios->gpios[0].port = 70;
gpios->gpios[0].polarity = ACTIVE_LOW;
- gpios->gpios[0].value = (gp_lvl3 >> (70 - 64)) & 1;
+ gpios->gpios[0].value = !get_write_protect_state();
strncpy((char *)gpios->gpios[0].name,"write protect", GPIO_MAX_NAME_LENGTH);
/* Recovery: Virtual GPIO in the EC (Servo GPIO68 active low) */
@@ -70,7 +67,7 @@ void fill_lb_gpios(struct lb_gpios *gpios)
/* Lid switch GPIO active high (open). */
gpios->gpios[3].port = 15;
gpios->gpios[3].polarity = ACTIVE_HIGH;
- gpios->gpios[3].value = ((gp_lvl >> 15) & 1);
+ gpios->gpios[3].value = get_lid_switch();
strncpy((char *)gpios->gpios[3].name,"lid", GPIO_MAX_NAME_LENGTH);
/* Power Button */
@@ -88,6 +85,22 @@ void fill_lb_gpios(struct lb_gpios *gpios)
}
#endif
+int get_lid_switch(void)
+{
+ device_t dev;
+#ifdef __PRE_RAM__
+ dev = PCI_DEV(0, 0x1f, 0);
+#else
+ dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
+#endif
+ u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
+
+ if (!gpio_base)
+ return 0;
+
+ u32 gp_lvl = inl(gpio_base + GP_LVL);
+ return (gp_lvl >> 15) & 1;
+}
int get_developer_mode_switch(void)
{
@@ -115,6 +128,24 @@ int get_developer_mode_switch(void)
return !((gp_lvl >> 17) & 1);
}
+int get_write_protect_state(void)
+{
+ device_t dev;
+#ifdef __PRE_RAM__
+ dev = PCI_DEV(0, 0x1f, 0);
+#else
+ dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
+#endif
+ u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
+
+ if (!gpio_base)
+ return 0;
+
+ u32 gp_lvl3 = inl(gpio_base + GP_LVL3);
+
+ return !((gp_lvl3 >> (70 - 64)) & 1);
+}
+
int get_recovery_mode_switch(void)
{
u8 rec_mode;