Remove another set of includes from Fam10 romstages:

northbridge/amd/amdht/ht_wrapper.c
northbridge/amd/amdfam10/raminit_amdmct.c
cpu/amd/model_10xxx/fidvid.c
pc80/mc146818rtc_early.c

They are now included by the fam10 chipset code that requires them.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5548 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

13 files changed, 13 insertions, 29 deletions

diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c
index 58d38cd603..4a1398a4d3 100644
--- a/src/cpu/amd/car/post_cache_as_ram.c
+++ b/src/cpu/amd/car/post_cache_as_ram.c
@@ -3,7 +3,9 @@
  */
 #include <string.h>
 #include <arch/stages.h>
+#include <cpu/x86/mtrr.h>
 #include "cpu/amd/car/disable_cache_as_ram.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
 
 static inline void print_debug_pcar(const char *strval, uint32_t val)
 {
diff --git a/src/cpu/amd/model_10xxx/fidvid.c b/src/cpu/amd/model_10xxx/fidvid.c
index cba7c2a908..c155cac8f7 100644
--- a/src/cpu/amd/model_10xxx/fidvid.c
+++ b/src/cpu/amd/model_10xxx/fidvid.c
@@ -18,7 +18,7 @@
  */
 
 #if SET_FIDVID == 1
-#include "../../../northbridge/amd/amdht/AsPsDefs.h"
+#include <northbridge/amd/amdht/AsPsDefs.h>
 
 #define SET_FIDVID_DEBUG 1
 
diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c
index a64cdd8874..48a32f8e26 100644
--- a/src/cpu/amd/model_10xxx/init_cpus.c
+++ b/src/cpu/amd/model_10xxx/init_cpus.c
@@ -25,6 +25,9 @@
 #include <northbridge/amd/amdht/AsPsDefs.h>
 #include <northbridge/amd/amdht/porting.h>
 
+#include <cpu/x86/mtrr/earlymtrr.c>
+#include <northbridge/amd/amdfam10/raminit_amdmct.c>
+
 //it takes the CONFIG_ENABLE_APIC_EXT_ID and CONFIG_APIC_ID_OFFSET and CONFIG_LIFT_BSP_APIC_ID
 #ifndef SET_FIDVID
 	#define SET_FIDVID 1
@@ -976,3 +979,5 @@ static void finalize_node_setup(struct sys_info *sysinfo)
 	}
 #endif
 }
+
+#include "fidvid.c"
diff --git a/src/cpu/amd/quadcore/quadcore.c b/src/cpu/amd/quadcore/quadcore.c
index 142a270125..cb256c4d7d 100644
--- a/src/cpu/amd/quadcore/quadcore.c
+++ b/src/cpu/amd/quadcore/quadcore.c
@@ -18,6 +18,8 @@
  */
 
 #include <console/console.h>
+#include <pc80/mc146818rtc_early.c>
+#include <northbridge/amd/amdht/ht_wrapper.c>
 
 #ifndef SET_NB_CFG_54
 	#define SET_NB_CFG_54 1
diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c
index de8058e308..fa08e357b3 100644
--- a/src/mainboard/amd/mahogany_fam10/romstage.c
+++ b/src/mainboard/amd/mahogany_fam10/romstage.c
@@ -46,7 +46,6 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
 #include <console/console.h>
 #include "lib/ramtest.c"
 #include <cpu/amd/model_10xxx_rev.h>
@@ -82,10 +81,8 @@ static int spd_read_byte(u32 device, u32 address)
 }
 
 #include "northbridge/amd/amdfam10/amdfam10.h"
-#include "northbridge/amd/amdht/ht_wrapper.c"
 
 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
-#include "northbridge/amd/amdfam10/raminit_amdmct.c"
 #include "northbridge/amd/amdfam10/amdfam10_pci.c"
 
 #include "resourcemap.c"
@@ -95,7 +92,6 @@ static int spd_read_byte(u32 device, u32 address)
 #include "cpu/amd/microcode/microcode.c"
 #include "cpu/amd/model_10xxx/update_microcode.c"
 #include "cpu/amd/model_10xxx/init_cpus.c"
-#include "cpu/amd/model_10xxx/fidvid.c"
 
 #include "northbridge/amd/amdfam10/early_ht.c"
 #include "southbridge/amd/sb700/sb700_early_setup.c"
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
index 17cee75840..038fbedff9 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
@@ -46,7 +46,6 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
 #include <console/console.h>
 #include "lib/ramtest.c"
 #include <cpu/amd/model_10xxx_rev.h>
@@ -104,10 +103,8 @@ static int spd_read_byte(u32 device, u32 address)
 }
 
 #include "northbridge/amd/amdfam10/amdfam10.h"
-#include "northbridge/amd/amdht/ht_wrapper.c"
 
 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
-#include "northbridge/amd/amdfam10/raminit_amdmct.c"
 #include "northbridge/amd/amdfam10/amdfam10_pci.c"
 
 #include "resourcemap.c"
@@ -117,7 +114,6 @@ static int spd_read_byte(u32 device, u32 address)
 #include "cpu/amd/microcode/microcode.c"
 #include "cpu/amd/model_10xxx/update_microcode.c"
 #include "cpu/amd/model_10xxx/init_cpus.c"
-#include "cpu/amd/model_10xxx/fidvid.c"
 
 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c
index d0bbaa4026..d8458d7fb1 100644
--- a/src/mainboard/amd/tilapia_fam10/romstage.c
+++ b/src/mainboard/amd/tilapia_fam10/romstage.c
@@ -46,7 +46,6 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
 #include <console/console.h>
 #include "lib/ramtest.c"
 #include <cpu/amd/model_10xxx_rev.h>
@@ -82,10 +81,8 @@ static int spd_read_byte(u32 device, u32 address)
 }
 
 #include "northbridge/amd/amdfam10/amdfam10.h"
-#include "northbridge/amd/amdht/ht_wrapper.c"
 
 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
-#include "northbridge/amd/amdfam10/raminit_amdmct.c"
 #include "northbridge/amd/amdfam10/amdfam10_pci.c"
 
 #include "resourcemap.c"
@@ -95,7 +92,6 @@ static int spd_read_byte(u32 device, u32 address)
 #include "cpu/amd/microcode/microcode.c"
 #include "cpu/amd/model_10xxx/update_microcode.c"
 #include "cpu/amd/model_10xxx/init_cpus.c"
-#include "cpu/amd/model_10xxx/fidvid.c"
 
 #include "northbridge/amd/amdfam10/early_ht.c"
 #include "southbridge/amd/sb700/sb700_early_setup.c"
diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c
index eb65924c86..1e44c86c5b 100644
--- a/src/mainboard/msi/ms9652_fam10/romstage.c
+++ b/src/mainboard/msi/ms9652_fam10/romstage.c
@@ -44,7 +44,6 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
 #include <console/console.h>
 #if CONFIG_USBDEBUG_DIRECT
 #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c"
@@ -88,10 +87,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 }
 
 #include "northbridge/amd/amdfam10/amdfam10.h"
-#include "northbridge/amd/amdht/ht_wrapper.c"
 
 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
-#include "northbridge/amd/amdfam10/raminit_amdmct.c"
 #include "northbridge/amd/amdfam10/amdfam10_pci.c"
 
 #include "resourcemap.c"
@@ -123,7 +120,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "cpu/amd/model_10xxx/update_microcode.c"
 #include "cpu/amd/model_10xxx/init_cpus.c"
 
-#include "cpu/amd/model_10xxx/fidvid.c"
 
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
index 35fae8d0e2..35b46485f4 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
@@ -42,7 +42,6 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
 
 #include <console/console.h>
 #include "lib/ramtest.c"
@@ -83,10 +82,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 }
 
 #include "northbridge/amd/amdfam10/amdfam10.h"
-#include "northbridge/amd/amdht/ht_wrapper.c"
 
 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
-#include "northbridge/amd/amdfam10/raminit_amdmct.c"
 #include "northbridge/amd/amdfam10/amdfam10_pci.c"
 
 #include "resourcemap.c"
@@ -108,7 +105,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "cpu/amd/model_10xxx/update_microcode.c"
 #include "cpu/amd/model_10xxx/init_cpus.c"
 
-#include "cpu/amd/model_10xxx/fidvid.c"
 
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c
index ff33819f32..f9c03767d6 100644
--- a/src/mainboard/supermicro/h8qme_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c
@@ -42,7 +42,6 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
 
 #include <console/console.h>
 #include "lib/ramtest.c"
@@ -86,10 +85,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 }
 
 #include "northbridge/amd/amdfam10/amdfam10.h"
-#include "northbridge/amd/amdht/ht_wrapper.c"
 
 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
-#include "northbridge/amd/amdfam10/raminit_amdmct.c"
 #include "northbridge/amd/amdfam10/amdfam10_pci.c"
 
 #include "resourcemap.c"
@@ -113,7 +110,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "cpu/amd/model_10xxx/update_microcode.c"
 #include "cpu/amd/model_10xxx/init_cpus.c"
 
-#include "cpu/amd/model_10xxx/fidvid.c"
 
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c
index b65ac2dd1e..5d54713ece 100644
--- a/src/mainboard/tyan/s2912_fam10/romstage.c
+++ b/src/mainboard/tyan/s2912_fam10/romstage.c
@@ -44,7 +44,6 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
 #include <console/console.h>
 #if CONFIG_USBDEBUG_DIRECT
 #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c"
@@ -88,10 +87,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 }
 
 #include "northbridge/amd/amdfam10/amdfam10.h"
-#include "northbridge/amd/amdht/ht_wrapper.c"
 
 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
-#include "northbridge/amd/amdfam10/raminit_amdmct.c"
 #include "northbridge/amd/amdfam10/amdfam10_pci.c"
 
 #include "resourcemap.c"
@@ -120,7 +117,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "cpu/amd/model_10xxx/update_microcode.c"
 #include "cpu/amd/model_10xxx/init_cpus.c"
 
-#include "cpu/amd/model_10xxx/fidvid.c"
 
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
diff --git a/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c b/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c
index b79448ec14..6feeacb58e 100644
--- a/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c
+++ b/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c
@@ -17,6 +17,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
+#include <delay.h>
 
 static void set_htic_bit(u8 i, u32 val, u8 bit)
 {
diff --git a/src/northbridge/amd/amdht/h3gtopo.h b/src/northbridge/amd/amdht/h3gtopo.h
index 00d46d01c5..b3f06f05ea 100644
--- a/src/northbridge/amd/amdht/h3gtopo.h
+++ b/src/northbridge/amd/amdht/h3gtopo.h
@@ -20,6 +20,8 @@
 #ifndef HTTOPO_H
 #define HTTOPO_H
 
+#include <stddef.h>
+
 /*----------------------------------------------------------------------------
  *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
  *