diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2015-08-31 10:01:03 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-09-08 11:32:29 +0000 |
| commit | cae067f136408ff2ab4972ea677a3f04e5892912 (patch) | |
| tree | 40ed6cfd40cb434edbff3fb2c28f2d8296e42b09 | |
| parent | 0d65df93f0d20da3cb78a88907f860062fe77a2a (diff) | |
| download | coreboot-cae067f136408ff2ab4972ea677a3f04e5892912.tar.xz | |
kunimitsu: Fix incorrect comment format in devicetree.cb
The devicetree.cb compiler can't handle C style /**/ comments,
they need to be shell-style #. Due to a last minute formatting
change in my commit to enable USB ports this broke the kunimitsu
build.
BUG=chrome-os-partner:44662
BRANCH=none
TEST=emerge-kunimitsu coreboot
Change-Id: I7a77f0f51345f779fcae43338cdc078bc91bb51c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6454b377f865ec3d4e426fce3259f4df5d513ef5
Original-Change-Id: I19bde397018890db37257b55d0481e0c9f3a41f2
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/296302
Original-Tested-by: Wenkai Du <wenkai.du@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11554
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
| -rw-r--r-- | src/mainboard/intel/kunimitsu/devicetree.cb | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index 1c3cf67749..5cc4f2ebc5 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -15,17 +15,17 @@ chip soc/intel/skylake [PchSerialIoIndexUart2] = PchSerialIoPci, \ }" - register "PortUsb20Enable[0]" = "1" /* Type-C Port 1 */ - register "PortUsb20Enable[1]" = "1" /* Type-C Port 2 */ - register "PortUsb20Enable[2]" = "1" /* Bluetooth */ - register "PortUsb20Enable[4]" = "1" /* Type-A Port (card) */ - register "PortUsb20Enable[6]" = "1" /* Camera */ - register "PortUsb20Enable[8]" = "1" /* Type-A Port (board) */ - - register "PortUsb30Enable[0]" = "1" /* Type-C Port 1 */ - register "PortUsb30Enable[1]" = "1" /* Type-C Port 2 */ - register "PortUsb30Enable[2]" = "1" /* Type-A Port (card) */ - register "PortUsb30Enable[3]" = "1" /* Type-A Port (board) */ + register "PortUsb20Enable[0]" = "1" # Type-C Port 1 + register "PortUsb20Enable[1]" = "1" # Type-C Port 2 + register "PortUsb20Enable[2]" = "1" # Bluetooth + register "PortUsb20Enable[4]" = "1" # Type-A Port (card) + register "PortUsb20Enable[6]" = "1" # Camera + register "PortUsb20Enable[8]" = "1" # Type-A Port (board) + + register "PortUsb30Enable[0]" = "1" # Type-C Port 1 + register "PortUsb30Enable[1]" = "1" # Type-C Port 2 + register "PortUsb30Enable[2]" = "1" # Type-A Port (card) + register "PortUsb30Enable[3]" = "1" # Type-A Port (board) register "pirqa_routing" = "0x8b" register "pirqb_routing" = "0x8a" |