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| author | Jonathan A. Kollasch <jakllsch@kollasch.net> | 2013-10-11 16:14:18 -0500 |
|---|---|---|
| committer | Jonathan A. Kollasch <jakllsch@kollasch.net> | 2013-10-14 02:22:07 +0200 |
| commit | cf18c856aafaaa2a7e5eaebf64a2d5c647e590e8 (patch) | |
| tree | 7e0b40e8a5defcf6eb7bdc9e934b91d57e118f6c | |
| parent | 948dede9c5a3d67295c4b9528fd11e741459c116 (diff) | |
| download | coreboot-cf18c856aafaaa2a7e5eaebf64a2d5c647e590e8.tar.xz | |
ck804: hide IOAPIC base address in PCI_BASE_ADDRESS_1
Linux unhelpfully "fixes" the value in PCI_BASE_ADDRESS_1 when it is
0xfec00000 (that is, outside the range of bus 0 address space). This
causes IOAPIC interrupts to fail to work under Linux. This issue was
originally unnoticed by me when testing as sanity checking such as
this is not done by NetBSD.
Hiding the IOAPIC BAR is done by the OEM BIOS on the ck804 boards I've
checked.
Change-Id: I736db163750f709d68c988fac075597a50b29ab7
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/3963
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
| -rw-r--r-- | src/southbridge/nvidia/ck804/lpc.c | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c index 4b33a3c58f..b3a9b00bc0 100644 --- a/src/southbridge/nvidia/ck804/lpc.c +++ b/src/southbridge/nvidia/ck804/lpc.c @@ -53,15 +53,10 @@ static void lpc_common_init(device_t dev) { - u8 byte; u32 dword; struct resource *res; /* I/O APIC initialization. */ - byte = pci_read_config8(dev, 0x74); - byte |= (1 << 0); /* Enable APIC. */ - pci_write_config8(dev, 0x74, byte); - res = find_resource(dev, PCI_BASE_ADDRESS_1); /* IOAPIC */ ASSERT(res != NULL); setup_ioapic(res->base, 0); /* Don't rename IOAPIC ID. */ @@ -221,6 +216,7 @@ static void ck804_lpc_read_resources(device_t dev) static void ck804_lpc_set_resources(device_t dev) { + u8 byte; struct resource *res; pci_dev_set_resources(dev); @@ -228,9 +224,15 @@ static void ck804_lpc_set_resources(device_t dev) /* APIC */ res = find_resource(dev, PCI_BASE_ADDRESS_1); if (res) { + byte = pci_read_config8(dev, 0x74); + byte |= (1 << 1); /* enable access to PCI_BASE_ADDRESS_1 */ + pci_write_config8(dev, 0x74, byte); pci_write_config32(dev, PCI_BASE_ADDRESS_1, res->base); res->flags |= IORESOURCE_STORED; report_resource_stored(dev, res, ""); + byte |= (1 << 0); /* enable decode of IOAPIC space */ + byte &= ~(1 << 1); /* hide PCI_BASE_ADDRESS_1 */ + pci_write_config8(dev, 0x74, byte); } /* HPET */ |