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| author | Subrata Banik <subrata.banik@intel.com> | 2017-07-31 10:44:09 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-08-03 20:30:09 +0000 |
| commit | d00d682670e1cf5c031a57274d7c4242f7a8193d (patch) | |
| tree | 9e018544bb385ad9647dc9042b4e81490d6bbeca | |
| parent | 4225493159bf1ad35e217d96de9c8222155e57fb (diff) | |
| download | coreboot-d00d682670e1cf5c031a57274d7c4242f7a8193d.tar.xz | |
soc/intel/skylake: Skip disabled IGD device
If IGD PCI device is disabled:
1. BAR for the device will be 0.
2. There is no need to allocate framebuffer for this device.
Some early SOCs don't have GFX model fuse by default hence
we need to add a check to ensure PCI device is enable. This
code to avoid die inside coreboot for missing resources.
Change-Id: Ic31d3e57ba730f6b569bf2cc3bdc54cb369b8caf
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
| -rw-r--r-- | src/soc/intel/skylake/igd.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/src/soc/intel/skylake/igd.c b/src/soc/intel/skylake/igd.c index dbcbd4d766..62bcf42267 100644 --- a/src/soc/intel/skylake/igd.c +++ b/src/soc/intel/skylake/igd.c @@ -36,7 +36,13 @@ uintptr_t fsp_soc_get_igd_bar(void) { - return find_resource(SA_DEV_IGD, PCI_BASE_ADDRESS_2)->base; + device_t dev = SA_DEV_IGD; + + /* Check if IGD PCI device is disabled */ + if (!dev->enabled) + return 0; + + return find_resource(dev, PCI_BASE_ADDRESS_2)->base; } u32 map_oprom_vendev(u32 vendev) |