diff options
author | Martin Roth <gaumless@gmail.com> | 2015-02-12 22:51:57 -0700 |
---|---|---|
committer | Martin Roth <gaumless@gmail.com> | 2015-03-12 20:35:49 +0100 |
commit | d08057aa20d8dff404ba9121a5d2052ae6575356 (patch) | |
tree | 72c3bd33b2ad4645916b70a7fac9d3d730de256c | |
parent | 48b3dbc7483f5404a2dfb3b8bb5f4bcf7d3c4b09 (diff) | |
download | coreboot-d08057aa20d8dff404ba9121a5d2052ae6575356.tar.xz |
intel/fsp_baytrail: Add PCI Root Port IRQ Routing
This change generates the ASL tables needed for the PCIe bridge routing.
It generates this ASL (swizzled for each of the 8 functions)
Name(RP1P, Package()
{
Package() {0x0000ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 },
Package() {0x0000ffff, 1, \_SB.PCI0.LPCB.LNKF, 0 },
Package() {0x0000ffff, 2, \_SB.PCI0.LPCB.LNKG, 0 },
Package() {0x0000ffff, 3, \_SB.PCI0.LPCB.LNKH, 0 },
})
Name(RP1A, Package()
{
Package() {0x0000ffff, 0, 0, 20 },
Package() {0x0000ffff, 1, 0, 21 },
Package() {0x0000ffff, 2, 0, 22 },
Package() {0x0000ffff, 3, 0, 23 },
})
Device(RP01) {
Name(_ADR, 0x1c0001)
Name(_PRW, Package() {
0, 0
})
Method(_PRT,0) {
If(PICM) {
Return (RP1A)
} Else {
Return (RP1P)
}
}
}
Change-Id: Id51261c11f8457fe2150f2b646aafc4fe1ffec30
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/8429
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
-rw-r--r-- | src/mainboard/intel/bayleybay_fsp/irqroute.h | 38 | ||||
-rw-r--r-- | src/mainboard/intel/minnowmax/irqroute.h | 38 | ||||
-rw-r--r-- | src/soc/intel/fsp_baytrail/acpi/irq_helper.h | 69 | ||||
-rw-r--r-- | src/soc/intel/fsp_baytrail/acpi/irqroute.asl | 7 | ||||
-rw-r--r-- | src/soc/intel/fsp_baytrail/baytrail/irq.h | 3 |
5 files changed, 123 insertions, 32 deletions
diff --git a/src/mainboard/intel/bayleybay_fsp/irqroute.h b/src/mainboard/intel/bayleybay_fsp/irqroute.h index 08552c534c..bce6f63bb6 100644 --- a/src/mainboard/intel/bayleybay_fsp/irqroute.h +++ b/src/mainboard/intel/bayleybay_fsp/irqroute.h @@ -40,22 +40,30 @@ *IR1Eh SIO INT(ABCD) - PIRQ BDEF *IR1Fh LPC INT(ABCD) - PIRQ HGBC */ + +/* PCIe bridge routing */ +#define BRIDGE1_DEV PCIE_DEV + +/* PCI bridge IRQs need to be updated in both tables and need to match */ +#define PCIE_BRIDGE_IRQ_ROUTES \ + PCIE_BRIDGE_DEV(RP, BRIDGE1_DEV, E, F, G, H) + #define PCI_DEV_PIRQ_ROUTES \ - PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(EMMC_DEV, D, E, F, G), \ - PCI_DEV_PIRQ_ROUTE(SDIO_DEV, B, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(SD_DEV, C, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(SATA_DEV, D, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(XHCI_DEV, E, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(LPE_DEV, F, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(MMC45_DEV, F, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(SIO1_DEV, B, A, D, C), \ - PCI_DEV_PIRQ_ROUTE(TXE_DEV, F, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(HDA_DEV, G, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(PCIE_DEV, E, F, G, H), \ - PCI_DEV_PIRQ_ROUTE(EHCI_DEV, D, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, D, E, F), \ - PCI_DEV_PIRQ_ROUTE(PCU_DEV, H, G, B, C) + PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(EMMC_DEV, D, E, F, G), \ + PCI_DEV_PIRQ_ROUTE(SDIO_DEV, B, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SD_DEV, C, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SATA_DEV, D, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(XHCI_DEV, E, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(LPE_DEV, F, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(MMC45_DEV, F, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SIO1_DEV, B, A, D, C), \ + PCI_DEV_PIRQ_ROUTE(TXE_DEV, F, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(HDA_DEV, G, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(BRIDGE1_DEV, E, F, G, H), \ + PCI_DEV_PIRQ_ROUTE(EHCI_DEV, D, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, D, E, F), \ + PCI_DEV_PIRQ_ROUTE(PCU_DEV, H, G, B, C) /* * Route each PIRQ[A-H] to a PIC IRQ[0-15] diff --git a/src/mainboard/intel/minnowmax/irqroute.h b/src/mainboard/intel/minnowmax/irqroute.h index 99c37767a4..a4dce3be0c 100644 --- a/src/mainboard/intel/minnowmax/irqroute.h +++ b/src/mainboard/intel/minnowmax/irqroute.h @@ -41,22 +41,30 @@ *IR1Eh SIO INT(ABCD) - PIRQ BDEF *IR1Fh LPC INT(ABCD) - PIRQ HGBC */ + +/* PCIe bridge routing */ +#define BRIDGE1_DEV PCIE_DEV + +/* PCI bridge IRQs need to be updated in both tables and need to match */ +#define PCIE_BRIDGE_IRQ_ROUTES \ + PCIE_BRIDGE_DEV(RP, BRIDGE1_DEV, E, F, G, H) + #define PCI_DEV_PIRQ_ROUTES \ - PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(EMMC_DEV, D, E, F, G), \ - PCI_DEV_PIRQ_ROUTE(SDIO_DEV, B, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(SD_DEV, C, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(SATA_DEV, D, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(XHCI_DEV, E, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(LPE_DEV, F, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(MMC45_DEV, F, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(SIO1_DEV, B, A, D, C), \ - PCI_DEV_PIRQ_ROUTE(TXE_DEV, F, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(HDA_DEV, G, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(PCIE_DEV, E, F, G, H), \ - PCI_DEV_PIRQ_ROUTE(EHCI_DEV, D, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, D, E, F), \ - PCI_DEV_PIRQ_ROUTE(PCU_DEV, H, G, B, C) + PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(EMMC_DEV, D, E, F, G), \ + PCI_DEV_PIRQ_ROUTE(SDIO_DEV, B, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SD_DEV, C, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SATA_DEV, D, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(XHCI_DEV, E, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(LPE_DEV, F, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(MMC45_DEV, F, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SIO1_DEV, B, A, D, C), \ + PCI_DEV_PIRQ_ROUTE(TXE_DEV, F, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(HDA_DEV, G, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(BRIDGE1_DEV, E, F, G, H), \ + PCI_DEV_PIRQ_ROUTE(EHCI_DEV, D, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, D, E, F), \ + PCI_DEV_PIRQ_ROUTE(PCU_DEV, H, G, B, C) /* * Route each PIRQ[A-H] to a PIC IRQ[0-15] diff --git a/src/soc/intel/fsp_baytrail/acpi/irq_helper.h b/src/soc/intel/fsp_baytrail/acpi/irq_helper.h index a0bcbabbbc..4e64ce7f5d 100644 --- a/src/soc/intel/fsp_baytrail/acpi/irq_helper.h +++ b/src/soc/intel/fsp_baytrail/acpi/irq_helper.h @@ -37,24 +37,89 @@ #undef PIRQ_PIC_ROUTES #undef PIRQ_PIC #undef IRQROUTE_H +#undef ROOTPORT_METHODS +#undef RP_METHOD +#undef ROOTPORT_IRQ_ROUTES +#undef RP_IRQ_ROUTES #if defined(PIC_MODE) #define ACPI_DEV_IRQ(dev_, pin_, pin_name_) \ Package() { ## dev_ ## ffff, pin_, \_SB.PCI0.LPCB.LNK ## pin_name_, 0 } +#define RP_IRQ_ROUTES(prefix_, func_, a_, b_, c_, d_) \ +Name(prefix_ ## func_ ## P, Package() \ +{ \ + ACPI_DEV_IRQ(0x0000, 0, a_), \ + ACPI_DEV_IRQ(0x0000, 1, b_), \ + ACPI_DEV_IRQ(0x0000, 2, c_), \ + ACPI_DEV_IRQ(0x0000, 3, d_), \ +}) + +/* define as blank so ROOTPORT_METHODS only gets inserted once */ +#define ROOTPORT_METHODS(prefix_, dev_) + #else /* defined(PIC_MODE) */ #define ACPI_DEV_IRQ(dev_, pin_, pin_name_) \ Package() { ## dev_ ## ffff, pin_, 0, PIRQ ## pin_name_ ## _APIC_IRQ } -#endif +#define RP_IRQ_ROUTES(prefix_, func_, a_, b_, c_, d_) \ +Name(prefix_ ## func_ ## A, Package() \ +{ \ + ACPI_DEV_IRQ(0x0000, 0, a_), \ + ACPI_DEV_IRQ(0x0000, 1, b_), \ + ACPI_DEV_IRQ(0x0000, 2, c_), \ + ACPI_DEV_IRQ(0x0000, 3, d_), \ +}) + +#define ROOTPORT_METHODS(prefix_, dev_) \ + RP_METHOD(prefix_, dev_, 0) \ + RP_METHOD(prefix_, dev_, 1) \ + RP_METHOD(prefix_, dev_, 2) \ + RP_METHOD(prefix_, dev_, 3) \ + RP_METHOD(prefix_, dev_, 4) \ + RP_METHOD(prefix_, dev_, 5) \ + RP_METHOD(prefix_, dev_, 6) \ + RP_METHOD(prefix_, dev_, 7) + +#endif /* defined(PIC_MODE) */ #define PCI_DEV_PIRQ_ROUTE(dev_, a_, b_, c_, d_) \ ACPI_DEV_IRQ(dev_, 0, a_), \ ACPI_DEV_IRQ(dev_, 1, b_), \ ACPI_DEV_IRQ(dev_, 2, c_), \ - ACPI_DEV_IRQ(dev_, 3, d_) + ACPI_DEV_IRQ(dev_, 3, d_), \ + +#define PCIE_BRIDGE_DEV(prefix_, dev_, a_, b_, c_, d_) \ + ROOTPORT_IRQ_ROUTES(prefix_, a_, b_, c_, d_) \ + ROOTPORT_METHODS(prefix_, dev_) + +#define ROOTPORT_IRQ_ROUTES(prefix_, a_, b_, c_, d_) \ + RP_IRQ_ROUTES(prefix_, 0, a_, b_, c_, d_) \ + RP_IRQ_ROUTES(prefix_, 1, b_, c_, d_, a_) \ + RP_IRQ_ROUTES(prefix_, 2, c_, d_, a_, b_) \ + RP_IRQ_ROUTES(prefix_, 3, d_, a_, b_, c_) \ + RP_IRQ_ROUTES(prefix_, 4, a_, b_, c_, d_) \ + RP_IRQ_ROUTES(prefix_, 5, b_, c_, d_, a_) \ + RP_IRQ_ROUTES(prefix_, 6, c_, d_, a_, b_) \ + RP_IRQ_ROUTES(prefix_, 7, d_, a_, b_, c_) + +#define RP_METHOD(prefix_, dev_, func_)\ +Device(prefix_ ## 0 ## func_) \ +{ \ + Name(_ADR, dev_ ## 000 ## func_) \ + Name(_PRW, Package() { \ + 0, 0 \ + }) \ + Method(_PRT,0) { \ + If(PICM) { \ + Return (prefix_ ## func_ ## A) \ + } Else { \ + Return (prefix_ ## func_ ## P) \ + } \ + } \ +} /* Empty PIRQ_PIC definition. */ #define PIRQ_PIC(pirq_, pic_irq_) diff --git a/src/soc/intel/fsp_baytrail/acpi/irqroute.asl b/src/soc/intel/fsp_baytrail/acpi/irqroute.asl index 940f853e5a..e6d7a5823d 100644 --- a/src/soc/intel/fsp_baytrail/acpi/irqroute.asl +++ b/src/soc/intel/fsp_baytrail/acpi/irqroute.asl @@ -40,4 +40,11 @@ Method(_PRT) PCI_DEV_PIRQ_ROUTES }) } + } + +PCIE_BRIDGE_IRQ_ROUTES +#undef PIC_MODE +#include "irq_helper.h" +PCIE_BRIDGE_IRQ_ROUTES + diff --git a/src/soc/intel/fsp_baytrail/baytrail/irq.h b/src/soc/intel/fsp_baytrail/baytrail/irq.h index 98ca116c57..6f56b1ffd9 100644 --- a/src/soc/intel/fsp_baytrail/baytrail/irq.h +++ b/src/soc/intel/fsp_baytrail/baytrail/irq.h @@ -160,6 +160,9 @@ extern const struct baytrail_irq_route global_baytrail_irq_route; #define PIRQ_PIC(pirq_, pic_irq_) \ [PIRQ ## pirq_] = PIRQ_PIC_IRQ ## pic_irq_ +/* used for ACPI only */ +#define PCIE_BRIDGE_DEV(prefix_, dev_, a_, b_, c_, d_) + #endif /* !defined(__ASSEMBLER__) && !defined(__ACPI__) */ #endif /* _BAYTRAIL_IRQ_H_ */ |