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authorKyösti Mälkki <kyosti.malkki@gmail.com>2016-06-15 06:15:46 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2016-06-17 00:22:10 +0200
commitd72cc4111b81497356b0cb5d4c305ae9e460a9b5 (patch)
treef27426f4bb9067d29426997089968b283c09d90a
parenta969ed34dbaebc595e298f60810669f0e8a3bcd2 (diff)
downloadcoreboot-d72cc4111b81497356b0cb5d4c305ae9e460a9b5.tar.xz
intel/model_206ax: Move platform specific defines
Change-Id: I3c517fc55dd333b1a457324f1d69aeb6f70acec2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15197 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
-rw-r--r--src/cpu/intel/model_206ax/cache_as_ram.inc2
-rw-r--r--src/include/cbmem.h13
-rw-r--r--src/northbridge/intel/sandybridge/sandybridge.h6
3 files changed, 9 insertions, 12 deletions
diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc
index 358ba75e04..56feab994e 100644
--- a/src/cpu/intel/model_206ax/cache_as_ram.inc
+++ b/src/cpu/intel/model_206ax/cache_as_ram.inc
@@ -17,8 +17,8 @@
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/post_code.h>
-#include <cbmem.h>
#include <arch/acpi.h>
+#include "northbridge/intel/sandybridge/sandybridge.h"
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
diff --git a/src/include/cbmem.h b/src/include/cbmem.h
index 2182ce7a46..5b75db0342 100644
--- a/src/include/cbmem.h
+++ b/src/include/cbmem.h
@@ -19,18 +19,12 @@
#include <commonlib/cbmem_id.h>
#include <rules.h>
-/* Delegation of resume backup memory so we don't have to
- * (slowly) handle backing up OS memory in romstage.c
- */
-#define CBMEM_BOOT_MODE 0x610
-#define CBMEM_RESUME_BACKUP 0x614
-#define CBMEM_FSP_HOB_PTR 0x614
-
-#ifndef __ASSEMBLER__
#include <stddef.h>
#include <stdint.h>
#include <boot/coreboot_tables.h>
+#define CBMEM_FSP_HOB_PTR 0x614
+
struct cbmem_entry;
/*
@@ -151,7 +145,4 @@ void set_top_of_ram(uint64_t ramtop);
void backup_top_of_ram(uint64_t ramtop);
#endif
-#endif /* __ASSEMBLER__ */
-
-
#endif /* _CBMEM_H_ */
diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h
index af5bd485e8..7b0efd1176 100644
--- a/src/northbridge/intel/sandybridge/sandybridge.h
+++ b/src/northbridge/intel/sandybridge/sandybridge.h
@@ -196,6 +196,12 @@
#define DMIDRCCFG 0xeb4 /* 32bit */
+/* Delegation of resume backup memory so we don't have to
+ * (slowly) handle backing up OS memory in romstage.c
+ */
+#define CBMEM_BOOT_MODE 0x610
+#define CBMEM_RESUME_BACKUP 0x614
+
#ifndef __ASSEMBLER__
static inline void barrier(void) { asm("" ::: "memory"); }