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authorMaxim Polyakov <max.senia.poliak@gmail.com>2019-05-06 11:54:21 +0300
committerPatrick Georgi <pgeorgi@google.com>2019-05-07 16:02:32 +0000
commitd7d0b04d3a0201bc7b2fed913bb623efe0158f81 (patch)
treee9d632f855a586b0e5a1885691e6d9cf37640ce2
parent551a75923ec7e7bacaf6da79b38eda5c3b3821ad (diff)
downloadcoreboot-d7d0b04d3a0201bc7b2fed913bb623efe0158f81.tar.xz
soc/skl/memmap: calculate mem size even if IGD undefined in devtree
The DRAM base memory should be calculated even if IGD isn`t defined in the board device tree Tested on Asrock H110M-DVS Change-Id: I3da51473e6c06da803bd969a4a6dff792c18f962 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32614 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
-rw-r--r--src/soc/intel/skylake/memmap.c19
1 files changed, 7 insertions, 12 deletions
diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c
index fde916a922..ff7edbc95a 100644
--- a/src/soc/intel/skylake/memmap.c
+++ b/src/soc/intel/skylake/memmap.c
@@ -170,13 +170,13 @@ static size_t get_prmrr_size(uintptr_t dram_base,
}
/* Calculate Intel Traditional Memory size based on GSM, DSM, TSEG and DPR. */
-static size_t calculate_traditional_mem_size(uintptr_t dram_base,
- const struct device *dev)
+static size_t calculate_traditional_mem_size(uintptr_t dram_base)
{
+ const struct device *igd_dev = pcidev_path_on_root(SA_DEVFN_IGD);
uintptr_t traditional_mem_base = dram_base;
size_t traditional_mem_size;
- if (dev->enabled) {
+ if (igd_dev && igd_dev->enabled) {
/* Read BDSM from Host Bridge */
traditional_mem_base -= sa_get_dsm_size();
@@ -200,9 +200,9 @@ static size_t calculate_traditional_mem_size(uintptr_t dram_base,
* Calculate Intel Reserved Memory size based on
* PRMRR size, Trace Hub config and PTT selection.
*/
-static size_t calculate_reserved_mem_size(uintptr_t dram_base,
- const struct device *dev)
+static size_t calculate_reserved_mem_size(uintptr_t dram_base)
{
+ const struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT);
uintptr_t reserve_mem_base = dram_base;
size_t reserve_mem_size;
const struct soc_intel_skylake_config *config;
@@ -259,20 +259,15 @@ static size_t calculate_reserved_mem_size(uintptr_t dram_base,
static uintptr_t calculate_dram_base(size_t *reserved_mem_size)
{
uintptr_t dram_base;
- const struct device *dev;
-
- dev = dev_find_slot(0, PCI_DEVFN(SA_DEV_SLOT_IGD, 0));
- if (!dev)
- die("ERROR - IGD device not found!");
/* Read TOLUD from Host Bridge offset */
dram_base = sa_get_tolud_base();
/* Get Intel Traditional Memory Range Size */
- dram_base -= calculate_traditional_mem_size(dram_base, dev);
+ dram_base -= calculate_traditional_mem_size(dram_base);
/* Get Intel Reserved Memory Range Size */
- *reserved_mem_size = calculate_reserved_mem_size(dram_base, dev);
+ *reserved_mem_size = calculate_reserved_mem_size(dram_base);
dram_base -= *reserved_mem_size;