diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2013-11-12 16:37:05 -0600 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-05-07 12:04:03 +0200 |
| commit | d7f0f3de10bb2aa4e41c8d87b364feaab7c1f704 (patch) | |
| tree | cd898d0e20d87f75a84d261d45837c286d545235 | |
| parent | 9547f8d799829ddab9196c4e0cad644a06db49e9 (diff) | |
| download | coreboot-d7f0f3de10bb2aa4e41c8d87b364feaab7c1f704.tar.xz | |
baytrail: add score and ssc iosf access functions
The SCORE allows controlling the pad configuration while
the SSC handles the configuration for the storage control
cluster.
BUG=chrome-os-partner:23966
BRANCH=None
TEST=Built.
Change-Id: Ifd9f67a4e88d5bb99faec6ceeb3e263001a87c41
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176533
Reviewed-by: Bernie Thompson <bhthompson@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4964
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
| -rw-r--r-- | src/soc/intel/baytrail/baytrail/iosf.h | 10 | ||||
| -rw-r--r-- | src/soc/intel/baytrail/iosf.c | 28 |
2 files changed, 38 insertions, 0 deletions
diff --git a/src/soc/intel/baytrail/baytrail/iosf.h b/src/soc/intel/baytrail/baytrail/iosf.h index 48d89b73f4..3a63d4a4a4 100644 --- a/src/soc/intel/baytrail/baytrail/iosf.h +++ b/src/soc/intel/baytrail/baytrail/iosf.h @@ -72,6 +72,10 @@ uint32_t iosf_lpss_read(int reg); void iosf_lpss_write(int reg, uint32_t val); uint32_t iosf_ccu_read(int reg); void iosf_ccu_write(int reg, uint32_t val); +uint32_t iosf_score_read(int reg); +void iosf_score_write(int reg, uint32_t val); +uint32_t iosf_scc_read(int reg); +void iosf_scc_write(int reg, uint32_t val); /* IOSF ports. */ #define IOSF_PORT_AUNIT 0x00 /* IO Arbiter unit */ @@ -84,7 +88,9 @@ void iosf_ccu_write(int reg, uint32_t val); #define IOSF_PORT_DUNIT_CH1 0x07 /* DUNIT Channel 1 */ #define IOSF_PORT_SYSMEMIO 0x0c /* System Memory IO */ #define IOSF_PORT_USBPHY 0x43 /* USB PHY */ +#define IOSF_PORT_SCORE 0x48 /* SCORE */ #define IOSF_PORT_USHPHY 0x61 /* USB XHCI PHY */ +#define IOSF_PORT_SCC 0x63 /* Storage Control Cluster */ #define IOSF_PORT_LPSS 0xa0 /* LPSS - Low Power Subsystem */ #define IOSF_PORT_SATAPHY 0xa3 /* SATA PHY */ #define IOSF_PORT_PCIEPHY 0xa3 /* PCIE PHY */ @@ -107,8 +113,12 @@ void iosf_ccu_write(int reg, uint32_t val); #define IOSF_OP_WRITE_SYSMEMIO (IOSF_OP_READ_SYSMEMIO | 1) #define IOSF_OP_READ_USBPHY 0x06 #define IOSF_OP_WRITE_USBPHY (IOSF_OP_READ_USBPHY | 1) +#define IOSF_OP_READ_SCORE 0x06 +#define IOSF_OP_WRITE_SCORE (IOSF_OP_READ_SCORE | 1) #define IOSF_OP_READ_USHPHY 0x06 #define IOSF_OP_WRITE_USHPHY (IOSF_OP_READ_USHPHY | 1) +#define IOSF_OP_READ_SCC 0x06 +#define IOSF_OP_WRITE_SCC (IOSF_OP_READ_SCC | 1) #define IOSF_OP_READ_LPSS 0x06 #define IOSF_OP_WRITE_LPSS (IOSF_OP_READ_LPSS | 1) #define IOSF_OP_READ_SATAPHY 0x00 diff --git a/src/soc/intel/baytrail/iosf.c b/src/soc/intel/baytrail/iosf.c index 7e0dacb812..4840deaede 100644 --- a/src/soc/intel/baytrail/iosf.c +++ b/src/soc/intel/baytrail/iosf.c @@ -168,3 +168,31 @@ void iosf_ccu_write(int reg, uint32_t val) IOSF_PORT(IOSF_PORT_CCU); return iosf_write_port(cr, reg, val); } + +uint32_t iosf_score_read(int reg) +{ + uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_SCORE) | + IOSF_PORT(IOSF_PORT_SCORE); + return iosf_read_port(cr, reg); +} + +void iosf_score_write(int reg, uint32_t val) +{ + uint32_t cr = IOSF_OPCODE(IOSF_OP_WRITE_SCORE) | + IOSF_PORT(IOSF_PORT_SCORE); + return iosf_write_port(cr, reg, val); +} + +uint32_t iosf_scc_read(int reg) +{ + uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_SCC) | + IOSF_PORT(IOSF_PORT_SCC); + return iosf_read_port(cr, reg); +} + +void iosf_scc_write(int reg, uint32_t val) +{ + uint32_t cr = IOSF_OPCODE(IOSF_OP_WRITE_SCC) | + IOSF_PORT(IOSF_PORT_SCC); + return iosf_write_port(cr, reg, val); +} |