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authorAaron Durbin <adurbin@chromium.org>2013-10-10 21:03:50 -0500
committerAaron Durbin <adurbin@google.com>2014-02-13 16:55:33 +0100
commitdc249f690a46f00ae11bedd080a749d6f1e8df3e (patch)
treeea44edc063549051eb5dbaebf7bb245ae86a8d6f
parent42283e7994b6519c4d1786b840d439fb90be4fb0 (diff)
downloadcoreboot-dc249f690a46f00ae11bedd080a749d6f1e8df3e.tar.xz
baytrail: add vboot ramstage verification
Add suport for verifying the ramstage with vboot during romstage execution. Along with this support select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM to cache the relocated ramstage 1MiB below the top end of the TSEG region. BUG=chrome-os-partner:23249 BRANCH=None TEST=Built and booted with CONFIG_VBOOT_VERIFY_FIRMWARE=y selected. Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I355f62469bdcca62b0a4468100effab0342dc8fc Reviewed-on: https://chromium-review.googlesource.com/172712 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/4880 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
-rw-r--r--src/soc/intel/baytrail/romstage/romstage.c28
1 files changed, 28 insertions, 0 deletions
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index 4228615333..4d74b53e3e 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -25,12 +25,15 @@
#include <console/console.h>
#include <cbmem.h>
#include <cpu/x86/mtrr.h>
+#include <ramstage_cache.h>
#include <romstage_handoff.h>
#include <timestamp.h>
+#include <vendorcode/google/chromeos/chromeos.h>
#include <baytrail/gpio.h>
#include <baytrail/iomap.h>
#include <baytrail/lpc.h>
#include <baytrail/pci_devs.h>
+#include <baytrail/reset.h>
#include <baytrail/romstage.h>
static inline uint64_t timestamp_get(void)
@@ -169,6 +172,9 @@ void asmlinkage romstage_after_car(void)
timestamp_add_now(TS_END_ROMSTAGE);
+ /* Run vboot verification if configured. */
+ vboot_verify_firmware(romstage_handoff_find_or_add());
+
/* Load the ramstage. */
copy_and_run();
while (1);
@@ -270,3 +276,25 @@ static void *setup_stack_and_mttrs(void)
return slot;
}
+
+struct ramstage_cache *ramstage_cache_location(long *size)
+{
+ char *smm_base;
+ /* 1MiB cache size */
+ const long cache_size = (1 << 20);
+
+ /* Ramstage cache lives in TSEG region which is the definition of
+ * cbmem_top(). */
+ smm_base = cbmem_top();
+ *size = cache_size;
+ return (void *)&smm_base[CONFIG_SMM_TSEG_SIZE - cache_size];
+}
+
+void ramstage_cache_invalid(struct ramstage_cache *cache)
+{
+#if CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE
+ /* Perform cold reset on invalid ramstage cache. */
+ cold_reset();
+#endif
+}
+