diff options
| author | Kenji Chen <kenji.chen@intel.com> | 2014-09-12 02:10:53 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-02 13:30:43 +0200 |
| commit | e237f5ac95edb227106a888738771755194c82cd (patch) | |
| tree | 0027705649a7718122b065d755576f66c4128371 | |
| parent | 6ecaf65bffde68d60a53aeeeb62db43c4fa6c5c9 (diff) | |
| download | coreboot-e237f5ac95edb227106a888738771755194c82cd.tar.xz | |
Baytrail: Change PCIe root disable algorithm
Disable Root Port0 only when there is no PCIe device
present on any root port.
BUG=None
TEST=Boot Rambi with PCIe installed/non-installed on RP0 to
confirm the RP0 is correctly enabled/disabled. However, I still
need someone to help check if RP0(no device) is still enabled
if there is device on other RPs since since I have no devices
having slots from RP1/2/3.
Change-Id: Iae552975250ed6f309c423b847621b8994172891
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: c5cef0b7c2c146f0d46ed49b75fd2ec8369210ce
Original-Change-Id: I7147569e78b2d1ecea070bc933773cdcae59f9e7
Original-Signed-off-by: Kenji Chen <kenji.chen@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/217791
Original-Tested-by: Ted Kuo <tedkuo@ami.com.tw>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9219
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
| -rw-r--r-- | src/soc/intel/baytrail/baytrail/pcie.h | 2 | ||||
| -rw-r--r-- | src/soc/intel/baytrail/pcie.c | 39 |
2 files changed, 38 insertions, 3 deletions
diff --git a/src/soc/intel/baytrail/baytrail/pcie.h b/src/soc/intel/baytrail/baytrail/pcie.h index f76d3da332..92ca3c8d7f 100644 --- a/src/soc/intel/baytrail/baytrail/pcie.h +++ b/src/soc/intel/baytrail/baytrail/pcie.h @@ -98,5 +98,5 @@ #define PHYCTL4 0x408 # define SQDIS (1 << 27) - +#define PCIE_ROOT_PORT_COUNT 4 #endif /* _BAYTRAIL_PCIE_H_ */ diff --git a/src/soc/intel/baytrail/pcie.c b/src/soc/intel/baytrail/pcie.c index 71b90ded47..f80a494a0b 100644 --- a/src/soc/intel/baytrail/pcie.c +++ b/src/soc/intel/baytrail/pcie.c @@ -155,6 +155,35 @@ static void check_port_enabled(device_t dev) } } +static u8 all_ports_no_dev_present(device_t dev) +{ + u8 func; + u8 temp = dev->path.pci.devfn; + u8 device_not_present = 1; + u8 data; + + for (func = 1; func < PCIE_ROOT_PORT_COUNT; func++) { + dev->path.pci.devfn &= ~0x7; + dev->path.pci.devfn |= func; + + /* is pcie device there */ + if (pci_read_config32(dev, 0) == 0xFFFFFFFF) + continue; + + data = pci_read_config8(dev, XCAP + 3) | (SI >> 24); + pci_write_config8(dev, XCAP + 3, data); + + /* is any device present */ + if ((pci_read_config32(dev, SLCTL_SLSTS) & PDS)) { + device_not_present = 0; + break; + } + } + + dev->path.pci.devfn = temp; + return device_not_present; +} + static void check_device_present(device_t dev) { /* Set slot implemented. */ @@ -163,8 +192,14 @@ static void check_device_present(device_t dev) /* No device present. */ if (!(pci_read_config32(dev, SLCTL_SLSTS) & PDS)) { printk(BIOS_DEBUG, "No PCIe device present.\n"); - reg_script_run_on_dev(dev, no_dev_behind_port); - dev->enabled = 0; + if (is_first_port(dev)) { + if (all_ports_no_dev_present(dev)) { + reg_script_run_on_dev(dev, no_dev_behind_port); + dev->enabled = 0; + } + } else { + dev->enabled = 0; + } } else if(!dev->enabled) { /* Port is disabled, but device present. Disable link. */ pci_write_config32(dev, LCTL, |