summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorPraveen Hodagatta Pranesh <praveenx.hodagatta.pranesh@intel.com>2019-11-27 13:47:09 +0800
committerPatrick Georgi <pgeorgi@google.com>2019-12-02 12:08:04 +0000
commite58eafc45a67a25ffd19b43d9bd845290a87b71c (patch)
treebd4a55bb8608d94e0e4b731b85e1a27efe85c21a
parentb7f30ad25f8803e8e88963550b7ff4eb0d86dcdb (diff)
downloadcoreboot-e58eafc45a67a25ffd19b43d9bd845290a87b71c.tar.xz
soc/intel/cannonlake: Fix compilation
Change MicrocodeRegionLength to MicrocodeRegionSize as per coffeelake FsptUpd.h. TEST= Build with CONFIG_USE_CANNONLAKE_FSP_CAR selected and boot test on coffeelake RVP. Change-Id: Iebbf5c34e289870a4d7abdd49fd81e4db236051a Signed-off-by: Praveen Hodagatta Pranesh <praveenx.hodagatta.pranesh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37265 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/soc/intel/cannonlake/bootblock/bootblock.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/cannonlake/bootblock/bootblock.c b/src/soc/intel/cannonlake/bootblock/bootblock.c
index 9f8539766c..6a6dd8be25 100644
--- a/src/soc/intel/cannonlake/bootblock/bootblock.c
+++ b/src/soc/intel/cannonlake/bootblock/bootblock.c
@@ -39,10 +39,10 @@ const FSPT_UPD temp_ram_init_params = {
* All SoC since Gen-4 has above mechanism in place to load microcode
* even before hitting CPU reset vector. Hence skipping FSP-T loading
* microcode after CPU reset by passing '0' value to
- * FSPT_UPD.MicrocodeRegionBase and FSPT_UPD.MicrocodeRegionLength.
+ * FSPT_UPD.MicrocodeRegionBase and FSPT_UPD.MicrocodeRegionSize.
*/
.MicrocodeRegionBase = 0,
- .MicrocodeRegionLength = 0,
+ .MicrocodeRegionSize = 0,
.CodeRegionBase =
(uint32_t)(0x100000000ULL - CONFIG_ROM_SIZE),
.CodeRegionSize = (uint32_t)CONFIG_ROM_SIZE,