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authorMarshall Dawson <marshalldawson3rd@gmail.com>2017-09-22 15:14:46 -0600
committerMartin Roth <martinroth@google.com>2017-09-30 20:34:28 +0000
commite9b862eb2c5918f097ff03498959e74130671c67 (patch)
tree494fb0ecd48c3212bfd1d68ea9ee9d85782df780
parent6746d3784fb0c1c79c71b3f1c24a2bf59f75a2d0 (diff)
downloadcoreboot-e9b862eb2c5918f097ff03498959e74130671c67.tar.xz
amd/stoneyridge: Use generic SMM command port values
Remove the old Hudson-specific SMM command port definitions and use the ones in cpu/x86/smm.h. Change-Id: I3de9a178e5f189ac1dbc921e41b69d47e3796a4f Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
-rw-r--r--src/soc/amd/stoneyridge/acpi.c8
-rw-r--r--src/soc/amd/stoneyridge/include/soc/southbridge.h7
-rw-r--r--src/soc/amd/stoneyridge/smihandler.c6
-rw-r--r--src/soc/amd/stoneyridge/southbridge.c4
4 files changed, 9 insertions, 16 deletions
diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c
index 78fd4b71d1..e6e785c1a8 100644
--- a/src/soc/amd/stoneyridge/acpi.c
+++ b/src/soc/amd/stoneyridge/acpi.c
@@ -24,13 +24,13 @@
#include <arch/acpigen.h>
#include <arch/io.h>
#include <arch/ioapic.h>
+#include <cpu/x86/smm.h>
#include <cbmem.h>
#include <device/device.h>
#include <device/pci.h>
#include <soc/acpi.h>
#include <soc/southbridge.h>
#include <soc/nvs.h>
-#include <soc/smi.h>
unsigned long acpi_fill_madt(unsigned long current)
{
@@ -88,9 +88,9 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
fadt->sci_int = 9; /* IRQ 09 - ACPI SCI */
if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {
- fadt->smi_cmd = ACPI_SMI_CTL_PORT;
- fadt->acpi_enable = ACPI_SMI_CMD_ENABLE;
- fadt->acpi_disable = ACPI_SMI_CMD_DISABLE;
+ fadt->smi_cmd = APM_CNT;
+ fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
+ fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
fadt->s4bios_req = 0; /* Not supported */
fadt->pstate_cnt = 0; /* Not supported */
fadt->cst_cnt = 0; /* Not supported */
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index 20edf5f4cc..9f353fbdfd 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -66,13 +66,6 @@
#define ACPI_GPE0_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x10) /* 8 bytes */
#define ACPI_CPU_CONTROL (STONEYRIDGE_ACPI_IO_BASE + 0x08) /* 6 bytes */
-#define ACPI_SMI_CTL_PORT 0xb2
-#define ACPI_SMI_CMD_CST_CONTROL 0xde
-#define ACPI_SMI_CMD_PST_CONTROL 0xad
-#define ACPI_SMI_CMD_DISABLE 0xbe
-#define ACPI_SMI_CMD_ENABLE 0xef
-#define ACPI_SMI_CMD_S4_REQ 0xc0
-
#define REV_STONEYRIDGE_A11 0x11
#define REV_STONEYRIDGE_A12 0x12
diff --git a/src/soc/amd/stoneyridge/smihandler.c b/src/soc/amd/stoneyridge/smihandler.c
index 9aff6905ee..45dada5227 100644
--- a/src/soc/amd/stoneyridge/smihandler.c
+++ b/src/soc/amd/stoneyridge/smihandler.c
@@ -27,15 +27,15 @@ enum smi_source {
static void sb_apmc_smi_handler(void)
{
u32 reg32;
- const uint8_t cmd = inb(ACPI_SMI_CTL_PORT);
+ const uint8_t cmd = inb(APM_CNT);
switch (cmd) {
- case ACPI_SMI_CMD_ENABLE:
+ case APM_CNT_ACPI_ENABLE:
reg32 = inl(ACPI_PM1_CNT_BLK);
reg32 |= (1 << 0); /* SCI_EN */
outl(reg32, ACPI_PM1_CNT_BLK);
break;
- case ACPI_SMI_CMD_DISABLE:
+ case APM_CNT_ACPI_DISABLE:
reg32 = inl(ACPI_PM1_CNT_BLK);
reg32 &= ~(1 << 0); /* clear SCI_EN */
outl(ACPI_PM1_CNT_BLK, reg32);
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index 5e36100281..1ca742f617 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -18,7 +18,7 @@
#include <arch/io.h>
#include <arch/acpi.h>
#include <bootstate.h>
-
+#include <cpu/x86/smm.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
@@ -79,7 +79,7 @@ static void sb_init_acpi_ports(void)
pm_write16(PM_CPU_CTRL, ACPI_CPU_CONTROL);
if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {
- pm_write16(PM_ACPI_SMI_CMD, ACPI_SMI_CTL_PORT);
+ pm_write16(PM_ACPI_SMI_CMD, APM_CNT);
enable_acpi_cmd_smi();
} else {
pm_write16(PM_ACPI_SMI_CMD, 0);