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authorMichał Żygowski <michal.zygowski@3mdeb.com>2018-10-24 16:57:47 +0200
committerPatrick Georgi <pgeorgi@google.com>2018-11-08 11:26:59 +0000
commiteaba51015c2c3356a7ff94cd0bb5088a548c4daa (patch)
tree3c651deb1cf91409734cff21d8dba428afb31da2
parentb66907ac16394e8d2eb4194199fd65a5c66e49fd (diff)
downloadcoreboot-eaba51015c2c3356a7ff94cd0bb5088a548c4daa.tar.xz
src/mb/pcengines/apu2/romstage.c: Allow coreboot console output on COM2
This change allows to redirect coreboot console output to COM2 by setting appropriate UART index in Console menu in Kconfig. Change is helpful for users which would like to use COM1 port for other purposes, because COM1 is the only port with hardware flow control. Change-Id: I39f88d7e7794f603775a985afe07fef349172e5f Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/29255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
-rw-r--r--src/mainboard/pcengines/apu2/romstage.c23
1 files changed, 23 insertions, 0 deletions
diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c
index fec25b4f60..3c5eed6bb5 100644
--- a/src/mainboard/pcengines/apu2/romstage.c
+++ b/src/mainboard/pcengines/apu2/romstage.c
@@ -19,6 +19,7 @@
#include <device/pci_ids.h>
#include <arch/io.h>
#include <arch/stages.h>
+#include <device/pnp.h>
#include <device/pnp_def.h>
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
@@ -32,10 +33,16 @@
#include <cpu/x86/bist.h>
#include <cpu/x86/lapic.h>
#include <southbridge/amd/pi/hudson/hudson.h>
+#include <superio/nuvoton/common/nuvoton.h>
+#include <superio/nuvoton/nct5104d/nct5104d.h>
#include <Fch/Fch.h>
#include "gpio_ftns.h"
+#define SIO_PORT 0x2e
+#define SERIAL1_DEV PNP_DEV(SIO_PORT, NCT5104D_SP1)
+#define SERIAL2_DEV PNP_DEV(SIO_PORT, NCT5104D_SP2)
+
static void early_lpc_init(void);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
@@ -56,6 +63,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
hudson_lpc_port80();
if (!cpu_init_detectedx && boot_cpu()) {
+ pci_devfn_t dev;
+ u32 data;
+
timestamp_init(timestamp_get());
timestamp_add_now(TS_START_ROMSTAGE);
@@ -64,6 +74,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
hudson_clk_output_48Mhz();
post_code(0x31);
+
+ dev = PCI_DEV(0, 0x14, 3);
+ data = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE);
+ /* enable 0x2e/0x4e IO decoding before configuring SuperIO */
+ pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, data | 3);
+
+ /* COM2 on apu5 is reserved so only COM1 should be supported */
+ if ((CONFIG_UART_FOR_CONSOLE == 1) &&
+ !IS_ENABLED(CONFIG_BOARD_PCENGINES_APU5))
+ nuvoton_enable_serial(SERIAL2_DEV, CONFIG_TTYS0_BASE);
+ else if (CONFIG_UART_FOR_CONSOLE == 0)
+ nuvoton_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE);
+
console_init();
}