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authorLin Huang <hl@rock-chips.com>2016-03-23 19:35:46 +0800
committerPatrick Georgi <pgeorgi@google.com>2016-05-09 08:44:19 +0200
commitef2eb9df6ced304b9c6a1b541697a52c88c53488 (patch)
treeeed8a99c8f0f1a5b2784edea6f693cc665430a95
parent92c2f5e38b0bb88235580ba98694a738e0f7bfa1 (diff)
downloadcoreboot-ef2eb9df6ced304b9c6a1b541697a52c88c53488.tar.xz
rockchip: rk3399: enable pwm
Reuse the rockchip common pwm driver. BRANCH=none BUG=chrome-os-partner:51537 TEST=emerge-kevin coreboot Change-Id: I1a1ab237f891f06affb74817b5cae1a034a9760e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 37afce0f94435ffef8bdd74b4251430f11ec22f4 Original-Change-Id: Ia94985f56e424d049fdcc5be86c696577d52a07c Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/333255 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14714 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
-rw-r--r--src/soc/rockchip/rk3399/Makefile.inc1
-rw-r--r--src/soc/rockchip/rk3399/include/soc/addressmap.h1
-rw-r--r--src/soc/rockchip/rk3399/include/soc/clock.h2
3 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/rockchip/rk3399/Makefile.inc b/src/soc/rockchip/rk3399/Makefile.inc
index bd6200f30a..773d87f32e 100644
--- a/src/soc/rockchip/rk3399/Makefile.inc
+++ b/src/soc/rockchip/rk3399/Makefile.inc
@@ -41,6 +41,7 @@ romstage-y += ../common/spi.c
romstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c
romstage-y += clock.c
romstage-y += mmu_operations.c
+romstage-y += ../common/pwm.c
romstage-y += timer.c
romstage-y += romstage.c
diff --git a/src/soc/rockchip/rk3399/include/soc/addressmap.h b/src/soc/rockchip/rk3399/include/soc/addressmap.h
index 90d1356298..30bb46495a 100644
--- a/src/soc/rockchip/rk3399/include/soc/addressmap.h
+++ b/src/soc/rockchip/rk3399/include/soc/addressmap.h
@@ -56,6 +56,7 @@
#define TSADC_BASE 0xff260000
#define SARADC_BASE 0xff100000
+#define RK_PWM_BASE 0xff420000
#define IC_BASES { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, \
I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE, I2C8_BASE }
diff --git a/src/soc/rockchip/rk3399/include/soc/clock.h b/src/soc/rockchip/rk3399/include/soc/clock.h
index 4c5a455a8b..ff4edb57ff 100644
--- a/src/soc/rockchip/rk3399/include/soc/clock.h
+++ b/src/soc/rockchip/rk3399/include/soc/clock.h
@@ -95,6 +95,8 @@ static struct rk3399_cru_reg * const cru_ptr = (void *)CRU_BASE;
#define PERILP1_HCLK_HZ (99000*KHz)
#define PERILP1_PCLK_HZ (49500*KHz)
+#define PWM_CLOCK_HZ PMU_PCLK_HZ
+
enum apll_l_frequencies {
APLL_L_1600_MHZ,
APLL_L_600_MHZ,