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| author | Marc Jones <marc.jones@se-eng.com> | 2012-06-15 23:03:15 -0600 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-07-24 21:40:44 +0200 |
| commit | ef6b08cc486e5d97103211dfeb3d629552a92e43 (patch) | |
| tree | 08bf1d16f212a746b517386c0c9c0cfbd56d8acb | |
| parent | d81744ea86b8f73bc404841e51aa1cf8d45ee9fb (diff) | |
| download | coreboot-ef6b08cc486e5d97103211dfeb3d629552a92e43.tar.xz | |
Add PCIe port disable debug message
The PCIe device enable function prints when it disables a device.
The PCIe ports(bridges) use a different routine that didn't print
the message. Add it to be consistent and to provide better debug
output.
Change-Id: I8462c48e7f4930db68703f0bfb710c01c9643a98
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/1326
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
| -rw-r--r-- | src/southbridge/intel/bd82x6x/pch.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c index 0913e1d2f1..3c448defd4 100644 --- a/src/southbridge/intel/bd82x6x/pch.c +++ b/src/southbridge/intel/bd82x6x/pch.c @@ -297,6 +297,8 @@ static void pch_pcie_enable(device_t dev) } if (!dev->enabled) { + printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); + /* * PCIE Power Savings for PantherPoint and CougarPoint/B1+ * |