intel/smm/gen1: Rename header file

Change-Id: I258fccc5e1db0bedb641c8af8cb9727954d4d7c1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

20 files changed, 34 insertions, 28 deletions

diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
index e47712c020..ce2b9e552f 100644
--- a/src/cpu/intel/model_1067x/model_1067x_init.c
+++ b/src/cpu/intel/model_1067x/model_1067x_init.c
@@ -24,7 +24,7 @@
 #include <cpu/intel/speedstep.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/name.h>
-#include <cpu/intel/smm/gen1/smi.h>
+#include <cpu/intel/smm_reloc.h>
 #include <cpu/intel/common/common.h>
 #include "chip.h"
 
diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c
index 73c9a4788e..312660b0c3 100644
--- a/src/cpu/intel/model_1067x/mp_init.c
+++ b/src/cpu/intel/model_1067x/mp_init.c
@@ -19,7 +19,7 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/mp.h>
 #include <cpu/intel/microcode.h>
-#include <cpu/intel/smm/gen1/smi.h>
+#include <cpu/intel/smm_reloc.h>
 #include <cpu/intel/common/common.h>
 #include <device/device.h>
 
diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c
index 2f10945c3b..b588095bf1 100644
--- a/src/cpu/intel/model_2065x/model_2065x_init.c
+++ b/src/cpu/intel/model_2065x/model_2065x_init.c
@@ -31,7 +31,7 @@
 #include <cpu/x86/name.h>
 #include "model_2065x.h"
 #include "chip.h"
-#include <cpu/intel/smm/gen1/smi.h>
+#include <cpu/intel/smm_reloc.h>
 #include <cpu/intel/common/common.h>
 
 /*
diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c
index d3aa52cf5d..4dbe4d91d2 100644
--- a/src/cpu/intel/model_206ax/model_206ax_init.c
+++ b/src/cpu/intel/model_206ax/model_206ax_init.c
@@ -32,7 +32,7 @@
 #include <pc80/mc146818rtc.h>
 #include "model_206ax.h"
 #include "chip.h"
-#include <cpu/intel/smm/gen1/smi.h>
+#include <cpu/intel/smm_reloc.h>
 #include <cpu/intel/common/common.h>
 
 /*
diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c
index f196706a36..8401611613 100644
--- a/src/cpu/intel/smm/gen1/smmrelocate.c
+++ b/src/cpu/intel/smm/gen1/smmrelocate.c
@@ -28,9 +28,9 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/smm.h>
 #include <cpu/intel/em64t101_save_state.h>
+#include <cpu/intel/smm_reloc.h>
 #include <console/console.h>
 #include <smp/node.h>
-#include "smi.h"
 
 #define SMRR_SUPPORTED (1 << 11)
 
diff --git a/src/cpu/intel/smm/gen1/smi.h b/src/include/cpu/intel/smm_reloc.h
index 6623bcc7cf..80094e73fc 100644
--- a/src/cpu/intel/smm/gen1/smi.h
+++ b/src/include/cpu/intel/smm_reloc.h
@@ -11,7 +11,10 @@
  * GNU General Public License for more details.
  */
 
-#include <device/device.h>
+#ifndef __INTEL_SMM_RELOC_H__
+#define __INTEL_SMM_RELOC_H__
+
+#include <types.h>
 
 /* These helpers are for performing SMM relocation. */
 void southbridge_smm_init(void);
@@ -19,14 +22,17 @@ u32 northbridge_get_tseg_base(void);
 u32 northbridge_get_tseg_size(void);
 void northbridge_write_smram(u8 smram);
 
-bool cpu_has_alternative_smrr(void);
+void smm_lock(void);
+void smm_relocate(void);
 
 /* parallel MP helper functions */
-void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
-		size_t *smm_save_state_size);
-void smm_initialize(void);
 void southbridge_smm_clear_state(void);
-void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
-			uintptr_t staggered_smbase);
-void smm_relocate(void);
-void smm_lock(void);
+
+/* To be removed. */
+void smm_initialize(void);
+void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size);
+void smm_relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase);
+
+bool cpu_has_alternative_smrr(void);
+
+#endif
diff --git a/src/northbridge/intel/gm45/memmap.c b/src/northbridge/intel/gm45/memmap.c
index 71037aedd0..ceb6476f5f 100644
--- a/src/northbridge/intel/gm45/memmap.c
+++ b/src/northbridge/intel/gm45/memmap.c
@@ -27,7 +27,7 @@
 #include <cbmem.h>
 #include <program_loading.h>
 #include <stage_cache.h>
-#include <cpu/intel/smm/gen1/smi.h>
+#include <cpu/intel/smm_reloc.h>
 #include "gm45.h"
 
 /*
diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c
index 1c01d307b2..384d98a54e 100644
--- a/src/northbridge/intel/gm45/northbridge.c
+++ b/src/northbridge/intel/gm45/northbridge.c
@@ -23,7 +23,7 @@
 #include <cpu/cpu.h>
 #include <boot/tables.h>
 #include <arch/acpi.h>
-#include <cpu/intel/smm/gen1/smi.h>
+#include <cpu/intel/smm_reloc.h>
 
 #include "chip.h"
 #include "gm45.h"
diff --git a/src/northbridge/intel/i945/memmap.c b/src/northbridge/intel/i945/memmap.c
index 6092c25770..f2518f45c9 100644
--- a/src/northbridge/intel/i945/memmap.c
+++ b/src/northbridge/intel/i945/memmap.c
@@ -24,7 +24,7 @@
 #include <cpu/intel/romstage.h>
 #include <cpu/x86/mtrr.h>
 #include <program_loading.h>
-#include <cpu/intel/smm/gen1/smi.h>
+#include <cpu/intel/smm_reloc.h>
 #include <stdint.h>
 #include <stage_cache.h>
 
diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c
index cd16958670..dd4e8ac125 100644
--- a/src/northbridge/intel/i945/northbridge.c
+++ b/src/northbridge/intel/i945/northbridge.c
@@ -23,7 +23,7 @@
 #include <stdlib.h>
 #include <cpu/cpu.h>
 #include <arch/acpi.h>
-#include <cpu/intel/smm/gen1/smi.h>
+#include <cpu/intel/smm_reloc.h>
 #include "i945.h"
 
 static int get_pcie_bar(u32 *base)
diff --git a/src/northbridge/intel/nehalem/memmap.c b/src/northbridge/intel/nehalem/memmap.c
index 031240c2f3..d592aea0b3 100644
--- a/src/northbridge/intel/nehalem/memmap.c
+++ b/src/northbridge/intel/nehalem/memmap.c
@@ -24,7 +24,7 @@
 #include <cpu/x86/mtrr.h>
 #include <program_loading.h>
 #include <stage_cache.h>
-#include <cpu/intel/smm/gen1/smi.h>
+#include <cpu/intel/smm_reloc.h>
 #include "nehalem.h"
 
 static uintptr_t smm_region_start(void)
diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c
index b6741a88fa..4ab89ad054 100644
--- a/src/northbridge/intel/nehalem/northbridge.c
+++ b/src/northbridge/intel/nehalem/northbridge.c
@@ -29,7 +29,7 @@
 #include <cpu/cpu.h>
 #include "chip.h"
 #include "nehalem.h"
-#include <cpu/intel/smm/gen1/smi.h>
+#include <cpu/intel/smm_reloc.h>
 
 static int bridge_revision_id = -1;
 
diff --git a/src/northbridge/intel/nehalem/smi.c b/src/northbridge/intel/nehalem/smi.c
index 5bfc934e04..8c19852043 100644
--- a/src/northbridge/intel/nehalem/smi.c
+++ b/src/northbridge/intel/nehalem/smi.c
@@ -19,7 +19,7 @@
 #include <device/pci_ops.h>
 #include "nehalem.h"
 
-#include <cpu/intel/smm/gen1/smi.h>
+#include <cpu/intel/smm_reloc.h>
 
 void northbridge_write_smram(u8 smram)
 {
diff --git a/src/northbridge/intel/pineview/memmap.c b/src/northbridge/intel/pineview/memmap.c
index 2e028892e3..8be63ef80e 100644
--- a/src/northbridge/intel/pineview/memmap.c
+++ b/src/northbridge/intel/pineview/memmap.c
@@ -25,7 +25,7 @@
 #include <northbridge/intel/pineview/pineview.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/intel/romstage.h>
-#include <cpu/intel/smm/gen1/smi.h>
+#include <cpu/intel/smm_reloc.h>
 #include <stdint.h>
 #include <stage_cache.h>
 
diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c
index 5a4eec6989..34cb583c49 100644
--- a/src/northbridge/intel/pineview/northbridge.c
+++ b/src/northbridge/intel/pineview/northbridge.c
@@ -25,7 +25,7 @@
 #include <boot/tables.h>
 #include <arch/acpi.h>
 #include <northbridge/intel/pineview/pineview.h>
-#include <cpu/intel/smm/gen1/smi.h>
+#include <cpu/intel/smm_reloc.h>
 
 /* Reserve everything between A segment and 1MB:
  *
diff --git a/src/northbridge/intel/sandybridge/memmap.c b/src/northbridge/intel/sandybridge/memmap.c
index 83a67abeb8..9e2e3333fe 100644
--- a/src/northbridge/intel/sandybridge/memmap.c
+++ b/src/northbridge/intel/sandybridge/memmap.c
@@ -20,7 +20,7 @@
 #include <cbmem.h>
 #include <console/console.h>
 #include <cpu/intel/romstage.h>
-#include <cpu/intel/smm/gen1/smi.h>
+#include <cpu/intel/smm_reloc.h>
 #include <cpu/x86/mtrr.h>
 #include <program_loading.h>
 #include <stage_cache.h>
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c
index 32b7a4cc2b..58f4a6812d 100644
--- a/src/northbridge/intel/sandybridge/northbridge.c
+++ b/src/northbridge/intel/sandybridge/northbridge.c
@@ -28,7 +28,7 @@
 #include <cpu/cpu.h>
 #include "chip.h"
 #include "sandybridge.h"
-#include <cpu/intel/smm/gen1/smi.h>
+#include <cpu/intel/smm_reloc.h>
 
 static int bridge_revision_id = -1;
 
diff --git a/src/northbridge/intel/x4x/memmap.c b/src/northbridge/intel/x4x/memmap.c
index a61d64e61d..9480fc05b0 100644
--- a/src/northbridge/intel/x4x/memmap.c
+++ b/src/northbridge/intel/x4x/memmap.c
@@ -28,7 +28,7 @@
 #include <cpu/x86/mtrr.h>
 #include <northbridge/intel/x4x/x4x.h>
 #include <program_loading.h>
-#include <cpu/intel/smm/gen1/smi.h>
+#include <cpu/intel/smm_reloc.h>
 #include <stage_cache.h>
 
 /** Decodes used Graphics Mode Select (GMS) to kilobytes. */
diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c
index f541e3ad48..ee705277cb 100644
--- a/src/northbridge/intel/x4x/northbridge.c
+++ b/src/northbridge/intel/x4x/northbridge.c
@@ -27,7 +27,7 @@
 #include <northbridge/intel/x4x/iomap.h>
 #include <northbridge/intel/x4x/chip.h>
 #include <northbridge/intel/x4x/x4x.h>
-#include <cpu/intel/smm/gen1/smi.h>
+#include <cpu/intel/smm_reloc.h>
 
 static const int legacy_hole_base_k = 0xa0000 / 1024;
 
diff --git a/src/southbridge/intel/common/smi.c b/src/southbridge/intel/common/smi.c
index 398c6804e0..dafb732d79 100644
--- a/src/southbridge/intel/common/smi.c
+++ b/src/southbridge/intel/common/smi.c
@@ -21,7 +21,7 @@
 #include <arch/io.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/smm.h>
-#include <cpu/intel/smm/gen1/smi.h>
+#include <cpu/intel/smm_reloc.h>
 #include <southbridge/intel/common/pmbase.h>
 #include <southbridge/intel/common/pmutil.h>