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authorTim Wawrzynczak <twawrzynczak@chromium.org>2019-10-25 15:13:04 -0600
committerPatrick Georgi <pgeorgi@google.com>2019-11-20 13:31:13 +0000
commitf2cae5085c49904b827d867dbf8d1a8b0d284c74 (patch)
treee9079a95865d34ade85bb653e7e9ef53dec11a82
parentbaeced336a2b0474b4396cd5e6be31c7c39c7a8e (diff)
downloadcoreboot-f2cae5085c49904b827d867dbf8d1a8b0d284c74.tar.xz
cpu/intel/car: Add EC software sync to Intel romstage
Perform EC software sync in romstage, before memory training is started. Because the ChromeOS EC will not currently perform USB-PD negotiation until it jumps to running its RW code, this allows the system to get access to more power earlier in the boot flow. This is guarded by CONFIG_VBOOT_EARLY_EC_SYNC. BUG=b:112198832 BRANCH=none TEST=EC software sync works in update and non-update case. No significant effect on boot time (~6 ms). Change-Id: I31f3407a2afcbf288461fab1397f965f025bc07c Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36211 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/cpu/intel/car/romstage.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c
index 1525233e39..9d196356e3 100644
--- a/src/cpu/intel/car/romstage.c
+++ b/src/cpu/intel/car/romstage.c
@@ -21,6 +21,7 @@
#include <commonlib/helpers.h>
#include <program_loading.h>
#include <timestamp.h>
+#include <security/vboot/vboot_common.h>
/* If we do not have a constrained _car_stack region size, use the
following as a guideline for acceptable stack usage. */
@@ -51,6 +52,9 @@ static void romstage_main(unsigned long bist)
for (i = 0; i < num_guards; i++)
stack_base[i] = stack_guard;
+ if (CONFIG(VBOOT_EARLY_EC_SYNC))
+ vboot_sync_ec();
+
mainboard_romstage_entry();
/* Check the stack. */