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authorFurquan Shaikh <furquan@chromium.org>2017-11-21 22:50:08 -0800
committerFurquan Shaikh <furquan@google.com>2017-11-30 20:31:43 +0000
commitf4c91e6613c523e5020da82d167f6102083b99e2 (patch)
tree139c64d0f50afb028561e36ce46765e4310a0eaa
parent4195b10d5267d7b48fc57cb9a50d6d6f48d73439 (diff)
downloadcoreboot-f4c91e6613c523e5020da82d167f6102083b99e2.tar.xz
mb/google/poppy/variants/nautilus: Disable DPTF
This change disables DPTF until the support is properly added in dptf.asl Change-Id: I68f2442e00718a4edbb34661d31d3a415d41c29f Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
-rw-r--r--src/mainboard/google/poppy/variants/nautilus/devicetree.cb3
-rw-r--r--src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/dptf.asl2
2 files changed, 1 insertions, 4 deletions
diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
index 5b60561f09..fe11a2e9d1 100644
--- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
@@ -21,9 +21,6 @@ chip soc/intel/skylake
# EC memory map range is 0x900-0x9ff
register "gen3_dec" = "0x00fc0901"
- # Enable DPTF
- register "dptf_enable" = "1"
-
# Enable S0ix
register "s0ix_enable" = "1"
diff --git a/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/dptf.asl b/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/dptf.asl
index a9ec74269f..216b76f157 100644
--- a/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/dptf.asl
+++ b/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/dptf.asl
@@ -13,4 +13,4 @@
* GNU General Public License for more details.
*/
-#include <baseboard/acpi/dptf.asl>
+/* Dummy file until DPTF support is added. */