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authorFurquan Shaikh <furquan@google.com>2015-08-05 17:05:26 -0700
committerPatrick Georgi <pgeorgi@google.com>2015-08-28 06:40:17 +0000
commitf8142155f9938beda215a3e1991f8544b4b1d690 (patch)
treec324524046f6a38e2f1f6ac4804f0c2a4205e9e3
parent0bdb88b106ec65e3d1296d61545e09ecdab0794f (diff)
downloadcoreboot-f8142155f9938beda215a3e1991f8544b4b1d690.tar.xz
t210: Pass in required BL31 parameters
BUG=chrome-os-partner:42989 BRANCH=None TEST=Compiles successfully and boots to kernel prompt. Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: ff42f0b4e7f81ea97e571ec03adac16b412e4a37 Original-Change-Id: If78857abfb9a348433b8707e58bea1f58416d243 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/291021 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-(cherry picked from commit 68eeb4bb4b817184eb42f4ee3a840317ede07dae) Original-Reviewed-on: https://chromium-review.googlesource.com/290988 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Change-Id: Id555198bc8e5d77f8ceee710d1a432516bd1ae4c Reviewed-on: http://review.coreboot.org/11382 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
-rw-r--r--src/soc/nvidia/tegra210/Makefile.inc1
-rw-r--r--src/soc/nvidia/tegra210/arm_tf.c47
2 files changed, 48 insertions, 0 deletions
diff --git a/src/soc/nvidia/tegra210/Makefile.inc b/src/soc/nvidia/tegra210/Makefile.inc
index 2d5bf583c1..0593f06e52 100644
--- a/src/soc/nvidia/tegra210/Makefile.inc
+++ b/src/soc/nvidia/tegra210/Makefile.inc
@@ -75,6 +75,7 @@ ramstage-$(CONFIG_MAINBOARD_DO_DSI_INIT) += mipi-phy.c
ramstage-$(CONFIG_MAINBOARD_DO_DSI_INIT) += ./jdi_25x18_display/panel-jdi-lpm102a188a.c
ramstage-$(CONFIG_MAINBOARD_DO_SOR_INIT) += dp.c
ramstage-$(CONFIG_MAINBOARD_DO_SOR_INIT) += sor.c
+ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += arm_tf.c
ramstage-y += sdram_lp0.c
ramstage-y += soc.c
diff --git a/src/soc/nvidia/tegra210/arm_tf.c b/src/soc/nvidia/tegra210/arm_tf.c
new file mode 100644
index 0000000000..56aa4acb5d
--- /dev/null
+++ b/src/soc/nvidia/tegra210/arm_tf.c
@@ -0,0 +1,47 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/cache.h>
+#include <arm_tf.h>
+#include <assert.h>
+#include <soc/addressmap.h>
+#include <stdlib.h>
+#include <string.h>
+#include <symbols.h>
+
+typedef struct bl31_plat_params {
+ uint32_t tzdram_size;
+} bl31_plat_params_t;
+
+static bl31_plat_params_t t210_plat_params;
+
+void *soc_get_bl31_plat_params(bl31_params_t *params)
+{
+ uintptr_t tz_base_mib;
+ size_t tz_size_mib;
+
+ carveout_range(CARVEOUT_TZ, &tz_base_mib, &tz_size_mib);
+
+ assert(tz_size_mib < 4096);
+ t210_plat_params.tzdram_size = tz_size_mib * MiB;
+
+ dcache_clean_by_mva(&t210_plat_params, sizeof(t210_plat_params));
+
+ return &t210_plat_params;
+}