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| author | Aaron Durbin <adurbin@chromium.org> | 2018-04-18 16:32:30 -0600 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2018-04-25 19:55:19 +0000 |
| commit | f8744425537f09738a153c8368364070be559f20 (patch) | |
| tree | a870af43905de216e97af7dd82f7f60ddc2d42ee | |
| parent | 0f35af8f4293d004d634c24fe029287b598326e9 (diff) | |
| download | coreboot-f8744425537f09738a153c8368364070be559f20.tar.xz | |
soc/intel/common: disable paging if PAGING_IN_CACHE_AS_RAM enabled
When tearing down cache-as-ram disable paging if PAGING_IN_CACHE_AS_RAM
is enabled.
BUG=b:72728953
Change-Id: I86e8a57a1187876dcbedce9f4f6b05be30aea7c6
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/25732
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
| -rw-r--r-- | src/soc/intel/common/block/cpu/car/exit_car.S | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/cpu/car/exit_car.S b/src/soc/intel/common/block/cpu/car/exit_car.S index 15e7f17358..86feddca43 100644 --- a/src/soc/intel/common/block/cpu/car/exit_car.S +++ b/src/soc/intel/common/block/cpu/car/exit_car.S @@ -22,6 +22,21 @@ .global chipset_teardown_car chipset_teardown_car: +#if IS_ENABLED(CONFIG_PAGING_IN_CACHE_AS_RAM) + /* + * Since Page table is located in CAR, disable paging before CAR + * teardown. Also clear CR3 and CR4.PAE. + */ + mov %cr0, %eax + and $(~(CR0_PG)), %eax + mov %eax, %cr0 + xor %eax, %eax + mov %eax, %cr3 + mov %cr4, %eax + and $(~(CR4_PAE)), %eax + mov %eax, %cr4 +#endif + /* * Retrieve return address from stack as it will get trashed below if * execution is utilizing the cache-as-ram stack. |