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authorTim Wawrzynczak <twawrzynczak@chromium.org>2019-09-18 14:10:31 -0600
committerPatrick Georgi <pgeorgi@google.com>2019-09-20 07:17:01 +0000
commitffd50a6e8d16191a438f48c0fcc61ae8f2f7c50c (patch)
tree895cf73a290b3920c8181244d6e44edbbdc8a96d
parent954111695cb7e27647ed9c150cac2f77d39c1e09 (diff)
downloadcoreboot-ffd50a6e8d16191a438f48c0fcc61ae8f2f7c50c.tar.xz
soc/intel/common/intelblocks: Remove PAD_CFG_GPI_GPIO_DRIVER_SCI
Intel's EDS says "1 = GPIO Driver Mode. GPIO input event updates are limited to GPI_STS. GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS updates are masked." Therefore, the GPI_GPIO_DRIVER_SCI option for pad configuration is meaningless, as any GPE will be masked if the GPIO driver is set as owner. Change-Id: Ia0cd0041dfc985cbe388cb89a4026038c7fb4383 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35460 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/soc/intel/common/block/include/intelblocks/gpio_defs.h7
1 files changed, 0 insertions, 7 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h
index d46e40420b..15df187d5b 100644
--- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h
+++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h
@@ -411,13 +411,6 @@
PAD_IOSSTATE(TxDRxE))
#if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT)
-/* GPI, GPIO Driver, SCI interrupt */
-#define PAD_CFG_GPI_GPIO_DRIVER_SCI(pad, pull, rst, trig, inv) \
- _PAD_CFG_STRUCT(pad, \
- PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \
- PAD_IRQ_CFG(SCI, trig, inv), \
- PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER | PAD_IOSSTATE(TxDRxE))
-
#define PAD_CFG_GPI_DUAL_ROUTE(pad, pull, rst, trig, inv, route1, route2) \
_PAD_CFG_STRUCT(pad, \
PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \