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authorLijian Zhao <lijian.zhao@intel.com>2018-12-06 22:53:44 -0800
committerPatrick Georgi <pgeorgi@google.com>2018-12-09 09:29:28 +0000
commitffe4aededf4b62db3da3a61a99a3ff3d447f61e2 (patch)
tree57dd7abe3e8a031791bdda04170ff418de6edb96
parentb1baa980ea2db879e6ec5ebf30bbdf16498d5afe (diff)
downloadcoreboot-ffe4aededf4b62db3da3a61a99a3ff3d447f61e2.tar.xz
mb/google/sarien: Enable LAN clock source usage
FSP defined a special clock source usage 0x70 for PCH LAN device, update that to google sarien platform. BUG=b:120003760 TEST=Boot up into OS, ethernet able to be listed in ifconfig. Change-Id: I9f945be4f0ce15470ab53f44e60143f3fd0fddf8 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/30100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
-rw-r--r--src/mainboard/google/sarien/variants/arcada/devicetree.cb2
-rw-r--r--src/mainboard/google/sarien/variants/sarien/devicetree.cb2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
index 93e0af978b..fccec9f3b6 100644
--- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
@@ -80,7 +80,7 @@ chip soc/intel/cannonlake
# PCIe port 9 for LAN
register "PcieRpEnable[8]" = "1"
- register "PcieClkSrcUsage[0]" = "8"
+ register "PcieClkSrcUsage[0]" = "PCIE_CLK_LAN"
register "PcieClkSrcClkReq[0]" = "0"
# PCIe port 10 for M.2 2230 WLAN
diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
index d25e725545..49200ad511 100644
--- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
@@ -85,7 +85,7 @@ chip soc/intel/cannonlake
# PCIe port 9 for LAN
register "PcieRpEnable[8]" = "1"
- register "PcieClkSrcUsage[3]" = "8"
+ register "PcieClkSrcUsage[3]" = "PCIE_CLK_LAN"
register "PcieClkSrcClkReq[3]" = "3"
# PCIe port 10 for M.2 2230 WLAN