summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorMaxim Polyakov <max.senia.poliak@gmail.com>2020-08-14 19:24:12 +0300
committerAngel Pons <th3fanbus@gmail.com>2020-09-24 11:52:00 +0000
commit0c5dd9febb8115d008d458409138480d95136d8c (patch)
tree1231fc46e9435ae84aaf9b45ad9cc5432605fec1
parentda3375ed41b9967699679734e980bede69b3b12b (diff)
downloadcoreboot-0c5dd9febb8115d008d458409138480d95136d8c.tar.xz
soc/intel/common/smbus: Add support for Apollo Lake SoC
Previously, SMBUS support was not required for Apollo Lake, since the SPD was read inside FSP-M, during memory initialization. However, the Kontron mAL-10 COMe module contains Nuvoton HWM chip that is connected to the processor via SMBUS. This patch adds SMBUS common driver support for Apollo Lake to initialize this HWM. TEST = After loading the nct7802 module on the Kontron mAL-10 with Linux OS, we can read the hwm registers, see temperature and fan speed: coretemp-isa-0000 Adapter: ISA adapter Package id 0: +52.0°C (high = +110.0°C, crit = +110.0°C) Core 0: +52.0°C (high = +110.0°C, crit = +110.0°C) Core 1: +52.0°C (high = +110.0°C, crit = +110.0°C) Core 2: +53.0°C (high = +110.0°C, crit = +110.0°C) Core 3: +53.0°C (high = +110.0°C, crit = +110.0°C) nct7802-i2c-0-2e Adapter: SMBus CMI adapter cmi in0: +3.35 V (min = +0.00 V, max = +4.09 V) in1: +1.92 V in3: +1.21 V (min = +0.00 V, max = +2.05 V) in4: +1.68 V (min = +0.00 V, max = +2.05 V) fan1: 0 RPM (min = 0 RPM) fan2: 1729 RPM (min = 0 RPM) fan3: 0 RPM (min = 0 RPM) temp1: +53.5°C (low = +0.0°C, high = +85.0°C) (crit = +100.0°C) sensor = thermistor temp4: +53.0°C (low = +0.0°C, high = +85.0°C) (crit = +100.0°C) temp6: +0.0°C Change-Id: I408ef84ede27a45fb057e22b2757fa6e66277ddd Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44475 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/include/device/pci_ids.h1
-rw-r--r--src/soc/intel/apollolake/Kconfig2
-rw-r--r--src/soc/intel/apollolake/include/soc/smbus.h2
-rw-r--r--src/soc/intel/common/block/smbus/smbus.c1
4 files changed, 6 insertions, 0 deletions
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index 83cf25e84d..e9674dffca 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -3755,6 +3755,7 @@
#define PCI_DEVICE_ID_INTEL_ADL_P_ID_8 0x4661
#define PCI_DEVICE_ID_INTEL_ADL_P_ID_9 0x467f
/* Intel SMBUS device Ids */
+#define PCI_DEVICE_ID_INTEL_APL_SMBUS 0x5ad4
#define PCI_DEVICE_ID_INTEL_SPT_LP_SMBUS 0x9d23
#define PCI_DEVICE_ID_INTEL_SPT_H_SMBUS 0xa123
#define PCI_DEVICE_ID_INTEL_LWB_SMBUS 0xa1a3
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index a30333bb68..d7ae7cb3e6 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -93,6 +93,8 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_SMM
select SOC_INTEL_COMMON_BLOCK_SPI
select SOC_INTEL_COMMON_BLOCK_CSE
+ select SOC_INTEL_COMMON_BLOCK_SMBUS
+ select SOUTHBRIDGE_INTEL_COMMON_SMBUS
select UDELAY_TSC
select TSC_MONOTONIC_TIMER
select PLATFORM_USES_FSP2_0
diff --git a/src/soc/intel/apollolake/include/soc/smbus.h b/src/soc/intel/apollolake/include/soc/smbus.h
index e08c02706b..e11119c485 100644
--- a/src/soc/intel/apollolake/include/soc/smbus.h
+++ b/src/soc/intel/apollolake/include/soc/smbus.h
@@ -17,4 +17,6 @@
#define TCO_INTRD_SEL_SMI (1 << 2)
#define TCO_INTRD_SEL_INT (1 << 1)
+#define SMBUS_SLAVE_ADDR 0x24
+
#endif
diff --git a/src/soc/intel/common/block/smbus/smbus.c b/src/soc/intel/common/block/smbus/smbus.c
index ae9f650246..8ba9d7a7b1 100644
--- a/src/soc/intel/common/block/smbus/smbus.c
+++ b/src/soc/intel/common/block/smbus/smbus.c
@@ -75,6 +75,7 @@ static struct device_operations smbus_ops = {
};
static const unsigned short pci_device_ids[] = {
+ PCI_DEVICE_ID_INTEL_APL_SMBUS,
PCI_DEVICE_ID_INTEL_CNL_SMBUS,
PCI_DEVICE_ID_INTEL_SPT_LP_SMBUS,
PCI_DEVICE_ID_INTEL_SPT_H_SMBUS,