diff options
| author | Vadim Bendebury <vbendeb@chromium.org> | 2015-03-31 11:47:16 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-22 08:51:47 +0200 |
| commit | 11ecdb75374c09b5fea69e55ef53dd5e0f789d93 (patch) | |
| tree | 799cbe4f0a509043fe7883f1d9f8587a9a9328c8 | |
| parent | 19ffcb3412d4fae370825c16b4bb0aaa0ed90ea9 (diff) | |
| download | coreboot-11ecdb75374c09b5fea69e55ef53dd5e0f789d93.tar.xz | |
imgtec/pistachio: increase RAM CBFS cache size
CBFS cache use is very close to the limit, does not allow to read much
more from CBFS.
BRANCH=none
BUG=chrome-os-partner:36586
TEST=the upcoming patches do not fail due to the lack of room in CBFS
cache any more
Change-Id: I8e784891e59ca284b3bd82557c2114a2f450d8a3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c94d55c8042db81c1eb0c10d5f24883e00cdc19a
Original-Change-Id: Ic09dbd5b4a0e165ccef396ff8a9e21b12c49b705
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/263268
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/9894
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
| -rw-r--r-- | src/soc/imgtec/pistachio/include/soc/memlayout.ld | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld index 802592f4d5..c7ea04bb94 100644 --- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld +++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld @@ -30,8 +30,8 @@ SECTIONS DRAM_START(0x00000000) /* DMA coherent area: accessed via KSEG1. */ DMA_COHERENT(0x00100000, 1M) - POSTRAM_CBFS_CACHE(0x00200000, 128K) - RAMSTAGE(0x00220000, 128K) + POSTRAM_CBFS_CACHE(0x00200000, 192K) + RAMSTAGE(0x00230000, 128K) /* * GRAM becomes the SRAM. Accessed through KSEG0 in the bootblock |