skylake: Add initial FSP2.0 support

Add Initial pieces of code to support fsp2.0 in skylake keeping
the fsp1.1 flow intact.

The soc/romstage.h and soc/ramstage.h have a reference to
fsp driver includes, so split these header files for
each version of FSP driver.

Add the below files,
car_stage.S:
	Add romstage entry point (car_stage_entry).
	This calls into romstage_fsp20.c and aslo handles
	the car teardown.
romstage_fsp20.c:
	Call fsp_memory_init() and also has the callback
	for filling memory init parameters.

Also add monotonic_timer.c to verstage.

With this patchset and relevant change in kunimitsu mainboard,
we are able to boot to romstage.

TEST= Build and Boot Kunimitsu with PLATFORM_USES_FSP1_1
Build and Boot Kunimitsu to romstage with PLATFORM_USES_FSP2_0

Change-Id: I4309c8d4369c84d2bd1b13e8ab7bfeaaec645520
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/16267
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)

17 files changed, 400 insertions, 48 deletions

diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 6171c41b27..edf5db31ee 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -42,6 +42,7 @@ config CPU_SPECIFIC_OPTIONS
 	select RTC
 	select SOC_INTEL_COMMON
 	select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
+	select SOC_INTEL_COMMON_GFX_OPREGION if PLATFORM_USES_FSP2_0
 	select SOC_INTEL_COMMON_LPSS_I2C
 	select SOC_INTEL_COMMON_NHLT
 	select SOC_INTEL_COMMON_RESET
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index 716c3d503f..aa3da61f22 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -40,12 +40,14 @@ romstage-y += pch.c
 romstage-y += pcr.c
 romstage-y += pei_data.c
 romstage-y += pmutil.c
+romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c
 romstage-y += smbus_common.c
 romstage-y += tsc_freq.c
 romstage-$(CONFIG_UART_DEBUG) += uart_debug.c
 
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
-ramstage-y += chip.c
+ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += chip.c
+ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += chip_fsp20.c
 ramstage-y += cpu.c
 ramstage-y += cpu_info.c
 ramstage-y += dsp.c
@@ -59,12 +61,14 @@ ramstage-y += lpc.c
 ramstage-y += me_status.c
 ramstage-y += memmap.c
 ramstage-y += monotonic_timer.c
+ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += opregion.c
 ramstage-y += pch.c
 ramstage-y += pcie.c
 ramstage-y += pcr.c
 ramstage-y += pei_data.c
 ramstage-y += pmc.c
 ramstage-y += pmutil.c
+ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c
 ramstage-y += ramstage.c
 ramstage-y += sd.c
 ramstage-y += smbus.c
@@ -93,7 +97,14 @@ smm-$(CONFIG_UART_DEBUG) += uart_debug.c
 
 CPPFLAGS_common += -I$(src)/soc/intel/skylake
 CPPFLAGS_common += -I$(src)/soc/intel/skylake/include
+
+ifeq ($(CONFIG_PLATFORM_USES_FSP1_1),y)
+CPPFLAGS_common += -I$(src)/soc/intel/skylake/include/fsp11
 CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1/skylake
+else
+CPPFLAGS_common += -I$(src)/soc/intel/skylake/include/fsp20
+CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/skykabylake
+endif
 
 # Currently used for microcode path.
 CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(MAINBOARD_DIR)
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
new file mode 100644
index 0000000000..215530cbdc
--- /dev/null
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <chip.h>
+#include <bootstate.h>
+#include <device/pci.h>
+#include <fsp/api.h>
+
+/* UPD parameters to be initialized before SiliconInit */
+void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *supd)
+{
+}
+
+struct pci_operations soc_pci_ops = {
+	/* TODO: Add set subsystem id function */
+};
+
diff --git a/src/soc/intel/skylake/igd.c b/src/soc/intel/skylake/igd.c
index a8ac645409..93f05cc150 100644
--- a/src/soc/intel/skylake/igd.c
+++ b/src/soc/intel/skylake/igd.c
@@ -24,7 +24,6 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <drivers/intel/gma/i915_reg.h>
-#include <fsp/gop.h>
 #include <soc/acpi.h>
 #include <soc/cpu.h>
 #include <soc/pm.h>
@@ -117,35 +116,10 @@ static void igd_init(struct device *dev)
 }
 
 /* Initialize IGD OpRegion, called from ACPI code */
-static int init_igd_opregion(igd_opregion_t *opregion)
+static int update_igd_opregion(igd_opregion_t *opregion)
 {
-	const optionrom_vbt_t *vbt;
-	uint32_t vbt_len;
 	u16 reg16;
 
-	memset(opregion, 0, sizeof(igd_opregion_t));
-
-	/* Read VBT table from flash */
-	vbt = fsp_get_vbt(&vbt_len);
-	if (!vbt)
-		die("vbt data not found");
-
-	memcpy(&opregion->header.signature, IGD_OPREGION_SIGNATURE,
-		sizeof(IGD_OPREGION_SIGNATURE) - 1);
-	memcpy(opregion->header.vbios_version, vbt->coreblock_biosbuild, sizeof(u32));
-	memcpy(opregion->vbt.gvd1, vbt, vbt->hdr_vbt_size <
-		sizeof(opregion->vbt.gvd1) ? vbt->hdr_vbt_size :
-		sizeof(opregion->vbt.gvd1));
-
-	/* Size, in KB, of the entire OpRegion structure (including header)*/
-	opregion->header.size = sizeof(igd_opregion_t) / KiB;
-	opregion->header.version = IGD_OPREGION_VERSION;
-
-	/* We just assume we're mobile for now */
-	opregion->header.mailboxes = MAILBOXES_MOBILE;
-
-	/* TODO Initialize Mailbox 1 */
-
 	/* Initialize Mailbox 3 */
 	opregion->mailbox3.bclp = IGD_BACKLIGHT_BRIGHTNESS;
 	opregion->mailbox3.pfit = IGD_FIELD_VALID | IGD_PFIT_STRETCH;
@@ -189,6 +163,7 @@ static unsigned long write_acpi_igd_opregion(device_t device,
 	printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n");
 	opregion = (igd_opregion_t *)current;
 	init_igd_opregion(opregion);
+	update_igd_opregion(opregion);
 	current += sizeof(igd_opregion_t);
 	current = acpi_align_current(current);
 
diff --git a/src/soc/intel/skylake/include/soc/ramstage.h b/src/soc/intel/skylake/include/fsp11/soc/ramstage.h
index 55f9972e4a..e469554ba2 100644
--- a/src/soc/intel/skylake/include/soc/ramstage.h
+++ b/src/soc/intel/skylake/include/fsp11/soc/ramstage.h
@@ -19,13 +19,18 @@
 
 #include <chip.h>
 #include <device/device.h>
+#include <fsp/gop.h>
 #include <fsp/ramstage.h>
+#include <fsp/soc_binding.h>
+
+#define FSP_SIL_UPD SILICON_INIT_UPD
+#define FSP_MEM_UPD MEMORY_INIT_UPD
 
 void pch_enable_dev(device_t dev);
 void soc_init_pre_device(void *chip_info);
 void soc_init_cpus(device_t dev);
 const char *soc_acpi_name(struct device *dev);
-
+int init_igd_opregion(igd_opregion_t *igd_opregion);
 extern struct pci_operations soc_pci_ops;
 
 #endif
diff --git a/src/soc/intel/skylake/include/soc/romstage.h b/src/soc/intel/skylake/include/fsp11/soc/romstage.h
index 6c40bd626d..6c40bd626d 100644
--- a/src/soc/intel/skylake/include/soc/romstage.h
+++ b/src/soc/intel/skylake/include/fsp11/soc/romstage.h
diff --git a/src/soc/intel/skylake/include/fsp20/soc/ramstage.h b/src/soc/intel/skylake/include/fsp20/soc/ramstage.h
new file mode 100644
index 0000000000..3a9d96bbdd
--- /dev/null
+++ b/src/soc/intel/skylake/include/fsp20/soc/ramstage.h
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_RAMSTAGE_H_
+#define _SOC_RAMSTAGE_H_
+
+#include <chip.h>
+#include <device/device.h>
+
+#include <fsp/api.h>
+#include <fsp/util.h>
+#include <soc/intel/common/opregion.h>
+
+#define FSP_SIL_UPD struct FSP_S_CONFIG
+#define FSP_MEM_UPD struct FSP_M_CONFIG
+
+void intel_silicon_init(void);
+void mainboard_silicon_init_params(struct FSP_S_CONFIG *params);
+void pch_enable_dev(device_t dev);
+void soc_init_pre_device(void *chip_info);
+void soc_init_cpus(device_t dev);
+const char *soc_acpi_name(struct device *dev);
+
+extern struct pci_operations soc_pci_ops;
+
+#endif
diff --git a/src/soc/intel/skylake/include/fsp20/soc/romstage.h b/src/soc/intel/skylake/include/fsp20/soc/romstage.h
new file mode 100644
index 0000000000..d48ac67ab3
--- /dev/null
+++ b/src/soc/intel/skylake/include/fsp20/soc/romstage.h
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015-2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_ROMSTAGE_H_
+#define _SOC_ROMSTAGE_H_
+
+#include <arch/cpu.h>
+#include <fsp/api.h>
+
+asmlinkage void *car_stage_c_entry(void);
+void mainboard_memory_init_params(struct FSPM_UPD *mupd);
+
+void systemagent_early_init(void);
+int smbus_read_byte(unsigned device, unsigned address);
+int early_spi_read_wpsr(u8 *sr);
+
+#endif /* _SOC_ROMSTAGE_H_ */
diff --git a/src/soc/intel/skylake/include/soc/smm.h b/src/soc/intel/skylake/include/soc/smm.h
index fa8da46f5a..1beaaa4986 100644
--- a/src/soc/intel/skylake/include/soc/smm.h
+++ b/src/soc/intel/skylake/include/soc/smm.h
@@ -20,7 +20,6 @@
 #include <stdint.h>
 #include <cpu/x86/msr.h>
 #include <fsp/memmap.h>
-#include <fsp/romstage.h>
 #include <soc/gpio.h>
 
 struct ied_header {
diff --git a/src/soc/intel/skylake/include/soc/vr_config.h b/src/soc/intel/skylake/include/soc/vr_config.h
index d70fd21304..1c19b8870e 100644
--- a/src/soc/intel/skylake/include/soc/vr_config.h
+++ b/src/soc/intel/skylake/include/soc/vr_config.h
@@ -19,7 +19,11 @@
 #ifndef _SOC_VR_CONFIG_H_
 #define _SOC_VR_CONFIG_H_
 
+#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)
 #include <fsp/soc_binding.h>
+#else
+#include <fsp/api.h>
+#endif
 
 struct vr_config {
 
@@ -74,7 +78,6 @@ enum vr_domain{
 	NUM_VR_DOMAINS
 };
 
-void fill_vr_domain_config(SILICON_INIT_UPD *params, int domain,
-				const struct vr_config *cfg);
-
+void fill_vr_domain_config(void *params,
+			int domain, const struct vr_config *cfg);
 #endif
diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c
index 6af13714a0..96debfd53f 100644
--- a/src/soc/intel/skylake/memmap.c
+++ b/src/soc/intel/skylake/memmap.c
@@ -21,7 +21,6 @@
 #include <device/pci.h>
 #include <soc/msr.h>
 #include <soc/pci_devs.h>
-#include <soc/romstage.h>
 #include <soc/smm.h>
 #include <soc/systemagent.h>
 #include <stdlib.h>
diff --git a/src/soc/intel/skylake/opregion.c b/src/soc/intel/skylake/opregion.c
new file mode 100644
index 0000000000..31987cb261
--- /dev/null
+++ b/src/soc/intel/skylake/opregion.c
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <soc/ramstage.h>
+#include <fsp/gop.h>
+#include <stdlib.h>
+#include <string.h>
+
+int init_igd_opregion(igd_opregion_t *opregion)
+{
+	const optionrom_vbt_t *vbt;
+	uint32_t vbt_len;
+
+	memset(opregion, 0, sizeof(igd_opregion_t));
+
+	/* Read VBT table from flash */
+	vbt = fsp_get_vbt(&vbt_len);
+	if (!vbt)
+		die("vbt data not found");
+
+	memcpy(&opregion->header.signature, IGD_OPREGION_SIGNATURE,
+		sizeof(IGD_OPREGION_SIGNATURE) - 1);
+	memcpy(opregion->header.vbios_version, vbt->coreblock_biosbuild, sizeof(u32));
+	memcpy(opregion->vbt.gvd1, vbt, vbt->hdr_vbt_size <
+		sizeof(opregion->vbt.gvd1) ? vbt->hdr_vbt_size :
+		sizeof(opregion->vbt.gvd1));
+
+	/* Size, in KB, of the entire OpRegion structure (including header)*/
+	opregion->header.size = sizeof(igd_opregion_t) / KiB;
+	opregion->header.version = IGD_OPREGION_VERSION;
+
+	/* We just assume we're mobile for now */
+	opregion->header.mailboxes = MAILBOXES_MOBILE;
+
+	return 0;
+}
diff --git a/src/soc/intel/skylake/reset.c b/src/soc/intel/skylake/reset.c
new file mode 100644
index 0000000000..ab251ce05f
--- /dev/null
+++ b/src/soc/intel/skylake/reset.c
@@ -0,0 +1,32 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <fsp/util.h>
+#include <reset.h>
+
+void chipset_handle_reset(enum fsp_status status)
+{
+	switch(status) {
+	case FSP_STATUS_RESET_REQUIRED_3: /* Global Reset */
+		printk(BIOS_DEBUG, "GLOBAL RESET!!\n");
+		hard_reset();
+		break;
+	default:
+		printk(BIOS_ERR, "unhandled reset type %x\n", status);
+		die("unknown reset type");
+		break;
+	}
+}
diff --git a/src/soc/intel/skylake/romstage/Makefile.inc b/src/soc/intel/skylake/romstage/Makefile.inc
index 31a452ff63..e552c396d4 100644
--- a/src/soc/intel/skylake/romstage/Makefile.inc
+++ b/src/soc/intel/skylake/romstage/Makefile.inc
@@ -1,7 +1,8 @@
-
 verstage-y += power_state.c
 
+romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += car_stage.S
 romstage-y += power_state.c
-romstage-y += romstage.c
+romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += romstage.c
+romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage_fsp20.c
 romstage-y += spi.c
 romstage-y += systemagent.c
diff --git a/src/soc/intel/skylake/romstage/car_stage.S b/src/soc/intel/skylake/romstage/car_stage.S
new file mode 100644
index 0000000000..c6401fa597
--- /dev/null
+++ b/src/soc/intel/skylake/romstage/car_stage.S
@@ -0,0 +1,131 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015-2016 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <rules.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/post_code.h>
+
+.section ".text"
+.global car_stage_entry
+
+car_stage_entry:
+
+	/* Enter the C code */
+	call	car_stage_c_entry
+
+/*
+ * Car teardown
+ */
+	/*
+	 * eax:  New stack address
+	 */
+
+	/* Switch to the stack in RAM */
+	movl	%eax, %esp
+
+	#include <soc/car_teardown.S>
+
+	/* Display the MTRRs */
+	call	soc_display_mtrrs
+
+	/*
+	 * The stack contents are initialized in src/soc/intel/common/stack.c
+	 * to be the following:
+	 *
+	 *		*
+	 *		*
+	 *		*
+	 *  +36: MTRR mask 1 63:32
+	 *  +32: MTRR mask 1 31:0
+	 *  +28: MTRR base 1 63:32
+	 *  +24: MTRR base 1 31:0
+	 *  +20: MTRR mask 0 63:32
+	 *  +16: MTRR mask 0 31:0
+	 *  +12: MTRR base 0 63:32
+	 *   +8: MTRR base 0 31:0
+	 *   +4: Number of MTRRs to setup (described above)
+	 *   +0: Number of variable MTRRs to clear
+	 */
+
+	/* Clear all of the variable MTRRs. */
+	popl	%ebx
+	movl	$MTRR_PHYS_BASE(0), %ecx
+	clr	%eax
+	clr	%edx
+
+1:
+	testl	%ebx, %ebx
+	jz	1f
+	wrmsr			/* Write MTRR base. */
+	inc	%ecx
+	wrmsr			/* Write MTRR mask. */
+	inc	%ecx
+	dec	%ebx
+	jmp	1b
+
+1:
+	/* Get number of MTRRs. */
+	popl	%ebx
+	movl	$MTRR_PHYS_BASE(0), %ecx
+2:
+	testl	%ebx, %ebx
+	jz	2f
+
+	/* Low 32 bits of MTRR base. */
+	popl	%eax
+	/* Upper 32 bits of MTRR base. */
+	popl	%edx
+	/* Write MTRR base. */
+	wrmsr
+	inc	%ecx
+	/* Low 32 bits of MTRR mask. */
+	popl	%eax
+	/* Upper 32 bits of MTRR mask. */
+	popl	%edx
+	/* Write MTRR mask. */
+	wrmsr
+	inc	%ecx
+
+	dec	%ebx
+	jmp	2b
+2:
+
+	post_code(0x39)
+
+	/* And enable cache again after setting MTRRs. */
+	movl	%cr0, %eax
+	andl	$~(CR0_CacheDisable | CR0_NoWriteThrough), %eax
+	movl	%eax, %cr0
+
+	post_code(0x3a)
+
+	/* Enable MTRR. */
+	movl	$MTRR_DEF_TYPE_MSR, %ecx
+	rdmsr
+	orl	$MTRR_DEF_TYPE_EN, %eax
+	wrmsr
+
+	post_code(0x3b)
+
+	/* Invalidate the cache again. */
+	invd
+
+__main:
+	post_code(POST_PREPARE_RAMSTAGE)
+	cld			/* Clear direction flag. */
+
+	call	copy_and_run
diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c
new file mode 100644
index 0000000000..8a15a69a23
--- /dev/null
+++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c
@@ -0,0 +1,44 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <fsp/util.h>
+#include <soc/romstage.h>
+
+asmlinkage void *car_stage_c_entry(void)
+{
+	bool s3wake = false;
+	console_init();
+	/* TODO: Add fill_powerstate and determine sleep state. */
+	fsp_memory_init(s3wake);
+	return NULL;
+}
+static void soc_memory_init_params(struct FSP_M_CONFIG *m_cfg)
+{
+	/* TODO: Fill SoC specific Memory init Params */
+}
+
+void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd){
+
+	struct FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
+
+	soc_memory_init_params(m_cfg);
+	mainboard_memory_init_params(mupd);
+}
+
+__attribute__((weak)) void mainboard_memory_init_params(struct FSPM_UPD *mupd)
+{
+	/* Do nothing */
+}
diff --git a/src/soc/intel/skylake/vr_config.c b/src/soc/intel/skylake/vr_config.c
index 40223e32cd..17ccd7dd93 100644
--- a/src/soc/intel/skylake/vr_config.c
+++ b/src/soc/intel/skylake/vr_config.c
@@ -14,6 +14,8 @@
  *
  */
 
+#include <fsp/api.h>
+#include <soc/ramstage.h>
 #include <soc/vr_config.h>
 
 /* Default values for domain configuration. PSI3 and PSI4 are disabled. */
@@ -80,9 +82,10 @@ static const struct vr_config default_configs[NUM_VR_DOMAINS] = {
 	},
 };
 
-void fill_vr_domain_config(SILICON_INIT_UPD *params, int domain,
-				const struct vr_config *chip_cfg)
+void fill_vr_domain_config(void *params,
+		int domain, const struct vr_config *chip_cfg)
 {
+	FSP_SIL_UPD *vr_params = (FSP_SIL_UPD *)params;
 	const struct vr_config *cfg;
 
 	if (domain < 0 || domain >= NUM_VR_DOMAINS)
@@ -94,14 +97,14 @@ void fill_vr_domain_config(SILICON_INIT_UPD *params, int domain,
 	else
 		cfg = &default_configs[domain];
 
-	params->VrConfigEnable[domain] = cfg->vr_config_enable;
-	params->Psi1Threshold[domain] = cfg->psi1threshold;
-	params->Psi2Threshold[domain] = cfg->psi2threshold;
-	params->Psi3Threshold[domain] = cfg->psi3threshold;
-	params->Psi3Enable[domain] = cfg->psi3enable;
-	params->Psi4Enable[domain] = cfg->psi4enable;
-	params->ImonSlope[domain] = cfg->imon_slope;
-	params->ImonOffset[domain] = cfg->imon_offset;
-	params->IccMax[domain] = cfg->icc_max;
-	params->VrVoltageLimit[domain] = cfg->voltage_limit;
+	vr_params->VrConfigEnable[domain] = cfg->vr_config_enable;
+	vr_params->Psi1Threshold[domain] = cfg->psi1threshold;
+	vr_params->Psi2Threshold[domain] = cfg->psi2threshold;
+	vr_params->Psi3Threshold[domain] = cfg->psi3threshold;
+	vr_params->Psi3Enable[domain] = cfg->psi3enable;
+	vr_params->Psi4Enable[domain] = cfg->psi4enable;
+	vr_params->ImonSlope[domain] = cfg->imon_slope;
+	vr_params->ImonOffset[domain] = cfg->imon_offset;
+	vr_params->IccMax[domain] = cfg->icc_max;
+	vr_params->VrVoltageLimit[domain] = cfg->voltage_limit;
 }