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| author | Ronald G. Minnich <rminnich@gmail.com> | 2006-04-18 20:42:58 +0000 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2006-04-18 20:42:58 +0000 |
| commit | 170ce333ca2d18df9ad1237dc9ac14e5ce235266 (patch) | |
| tree | 26735f4edc25723e99ef0ec9e72f3ac7b0e14f02 | |
| parent | df46cb205d57a91aa0fff142b2dd951e7731731b (diff) | |
| download | coreboot-170ce333ca2d18df9ad1237dc9ac14e5ce235266.tar.xz | |
add ram resources
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2256 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
| -rw-r--r-- | src/mainboard/olpc/rev_a/auto.c | 30 | ||||
| -rw-r--r-- | src/northbridge/amd/gx2/northbridge.c | 4 |
2 files changed, 25 insertions, 9 deletions
diff --git a/src/mainboard/olpc/rev_a/auto.c b/src/mainboard/olpc/rev_a/auto.c index ac9c2e5222..4775b8c9fe 100644 --- a/src/mainboard/olpc/rev_a/auto.c +++ b/src/mainboard/olpc/rev_a/auto.c @@ -37,6 +37,24 @@ static inline unsigned int fls(unsigned int x) return r; } + + + +/* sdram parameters for OLPC: + row address = 13 + col address = 9 + banks = 4 + dimm0size=128MB + d0_MB=1 (module banks) + d0_cb=4 (component banks) + do_psz=4KB (page size) + Trc=10 (clocks) + Tras=7 + Trcd=3 + Trp=3 + Trrd=2 + Tref=17.8ms + */ static void sdram_set_spd_registers(const struct mem_controller *ctrl) { /* Total size of DIMM = 2^row address (byte 3) * 2^col address (byte 4) * @@ -50,21 +68,17 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) msr = rdmsr(MC_CF07_DATA); /* get module banks (sides) per dimm, SPD byte 5 */ - module_banks = spd_read_byte(0xA0, 5); - if (module_banks < 1 || module_banks > 2) - print_err("Module banks per dimm\r\n"); + module_banks = 1; module_banks >>= 1; msr.hi &= ~(1 << CF07_UPPER_D0_MB_SHIFT); msr.hi |= (module_banks << CF07_UPPER_D0_MB_SHIFT); /* get component banks per module bank, SPD byte 17 */ - val = spd_read_byte(0xA0, 17); - if (val < 2 || val > 4) - print_err("Component banks per module bank\r\n"); + val = 4; val >>= 2; msr.hi &= ~(0x1 << CF07_UPPER_D0_CB_SHIFT); msr.hi |= (val << CF07_UPPER_D0_CB_SHIFT); - +HERE /* get the module bank density, SPD byte 31 */ val = spd_read_byte(0xA0, 31); val = fls(val); @@ -137,7 +151,7 @@ static void msr_init(void) #endif } - + static void main(unsigned long bist) { static const struct mem_controller memctrl [] = { diff --git a/src/northbridge/amd/gx2/northbridge.c b/src/northbridge/amd/gx2/northbridge.c index 7c3cb52623..981d5375e1 100644 --- a/src/northbridge/amd/gx2/northbridge.c +++ b/src/northbridge/amd/gx2/northbridge.c @@ -236,10 +236,11 @@ setup_gx2(void) static void optimize_xbus(device_t dev) { /* Optimise X-Bus performance */ - pci_write_config8(dev, 0x40, 0x1e); +/* pci_write_config8(dev, 0x40, 0x1e); pci_write_config8(dev, 0x41, 0x52); pci_write_config8(dev, 0x43, 0xc1); pci_write_config8(dev, 0x44, 0x00); +*/ } static void enable_shadow(device_t dev) @@ -433,6 +434,7 @@ static void enable_dev(struct device *dev) do_vsmbios(); dev->ops = &pci_domain_ops; pci_set_method(dev); + ram_resource(dev, 0, 0, sizeram()*1024); } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) { printk_debug("DEVICE_PATH_APIC_CLUSTER\n"); |