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| author | Vaibhav Shankar <vaibhav.shankar@intel.com> | 2016-10-14 16:08:32 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-10-18 03:32:25 +0200 |
| commit | 1ac773fa55195b1fd39eeb5ed83b302b04151c58 (patch) | |
| tree | b397f2cddceb8b6fcd16cce37971122e5c21b3e5 | |
| parent | 58caa8ba8c2871a26f878e181f16ec073779770c (diff) | |
| download | coreboot-1ac773fa55195b1fd39eeb5ed83b302b04151c58.tar.xz | |
mainboard/google/reef: Configure PERST pin for reef DVT
Configure GPIO 122 as PERST on DVT. This is to assert WiFi PERST
during s0ix entry.
BUG=chrome-os-partner:55877
TEST=S0ix functional on DVT
Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Change-Id: Iab18b2de621a1a9226c78493f6defa15081db875
Reviewed-on: https://review.coreboot.org/17030
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
| -rw-r--r-- | src/mainboard/google/reef/variants/baseboard/devicetree.cb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb index f393019737..00df9bd4b9 100644 --- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb @@ -15,7 +15,7 @@ chip soc/intel/apollolake # GPIO for PERST_0 # If the Board has PERST_0 signal, assign the GPIO # If the Board does not have PERST_0, assign GPIO_PRT0_UDEF - register "prt0_gpio" = "GPIO_PRT0_UDEF" + register "prt0_gpio" = "GPIO_122" # EMMC TX DATA Delay 1 # Refer to EDS-Vol2-22.3. |