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authorMatt DeVillier <matt.devillier@gmail.com>2020-03-31 17:37:12 -0500
committerMatt DeVillier <matt.devillier@gmail.com>2020-04-03 16:25:43 +0000
commit1d6e07348a6ea52396273d4617cdf0d4020760c4 (patch)
treee08bdc440695cde46fac6ae8a39f79af80611d72
parentc0b028f205a78ecc748e69d62450b4a804784da9 (diff)
downloadcoreboot-1d6e07348a6ea52396273d4617cdf0d4020760c4.tar.xz
mb/google/rambi: Convert to use override devicetree
Since the variants' devicetrees are almost identical, convert to using an overridetree setup for simplicity. Change-Id: I52b71cf12a4e0b67135cfb106c3e89b00205d3bc Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39996 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/mainboard/google/rambi/Kconfig4
-rw-r--r--src/mainboard/google/rambi/devicetree.cb (renamed from src/mainboard/google/rambi/variants/quawks/devicetree.cb)3
-rw-r--r--src/mainboard/google/rambi/variants/banjo/devicetree.cb104
-rw-r--r--src/mainboard/google/rambi/variants/banjo/overridetree.cb11
-rw-r--r--src/mainboard/google/rambi/variants/candy/devicetree.cb105
-rw-r--r--src/mainboard/google/rambi/variants/candy/overridetree.cb11
-rw-r--r--src/mainboard/google/rambi/variants/clapper/devicetree.cb101
-rw-r--r--src/mainboard/google/rambi/variants/clapper/overridetree.cb8
-rw-r--r--src/mainboard/google/rambi/variants/enguarde/devicetree.cb104
-rw-r--r--src/mainboard/google/rambi/variants/enguarde/overridetree.cb9
-rw-r--r--src/mainboard/google/rambi/variants/glimmer/devicetree.cb101
-rw-r--r--src/mainboard/google/rambi/variants/glimmer/overridetree.cb7
-rw-r--r--src/mainboard/google/rambi/variants/gnawty/devicetree.cb104
-rw-r--r--src/mainboard/google/rambi/variants/gnawty/overridetree.cb9
-rw-r--r--src/mainboard/google/rambi/variants/heli/devicetree.cb105
-rw-r--r--src/mainboard/google/rambi/variants/heli/overridetree.cb11
-rw-r--r--src/mainboard/google/rambi/variants/kip/devicetree.cb104
-rw-r--r--src/mainboard/google/rambi/variants/kip/overridetree.cb9
-rw-r--r--src/mainboard/google/rambi/variants/ninja/devicetree.cb105
-rw-r--r--src/mainboard/google/rambi/variants/ninja/overridetree.cb12
-rw-r--r--src/mainboard/google/rambi/variants/orco/devicetree.cb104
-rw-r--r--src/mainboard/google/rambi/variants/orco/overridetree.cb9
-rw-r--r--src/mainboard/google/rambi/variants/quawks/overridetree.cb6
-rw-r--r--src/mainboard/google/rambi/variants/rambi/devicetree.cb105
-rw-r--r--src/mainboard/google/rambi/variants/rambi/overridetree.cb12
-rw-r--r--src/mainboard/google/rambi/variants/squawks/devicetree.cb101
-rw-r--r--src/mainboard/google/rambi/variants/squawks/overridetree.cb6
-rw-r--r--src/mainboard/google/rambi/variants/sumo/devicetree.cb105
-rw-r--r--src/mainboard/google/rambi/variants/sumo/overridetree.cb13
-rw-r--r--src/mainboard/google/rambi/variants/swanky/devicetree.cb104
-rw-r--r--src/mainboard/google/rambi/variants/swanky/overridetree.cb9
-rw-r--r--src/mainboard/google/rambi/variants/winky/devicetree.cb105
-rw-r--r--src/mainboard/google/rambi/variants/winky/overridetree.cb13
33 files changed, 158 insertions, 1561 deletions
diff --git a/src/mainboard/google/rambi/Kconfig b/src/mainboard/google/rambi/Kconfig
index 7a23a7d09a..d820875718 100644
--- a/src/mainboard/google/rambi/Kconfig
+++ b/src/mainboard/google/rambi/Kconfig
@@ -64,9 +64,9 @@ config MAINBOARD_PART_NUMBER
default "Swanky" if BOARD_GOOGLE_SWANKY
default "Winky" if BOARD_GOOGLE_WINKY
-config DEVICETREE
+config OVERRIDE_DEVICETREE
string
- default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb"
+ default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
config EC_GOOGLE_CHROMEEC_BOARDNAME
string
diff --git a/src/mainboard/google/rambi/variants/quawks/devicetree.cb b/src/mainboard/google/rambi/devicetree.cb
index ee0f38d498..dc11ec8a91 100644
--- a/src/mainboard/google/rambi/variants/quawks/devicetree.cb
+++ b/src/mainboard/google/rambi/devicetree.cb
@@ -13,7 +13,6 @@ chip soc/intel/baytrail
register "usb3_port_disable_mask" = "0x0"
# USB PHY settings
- # TODO: These values are from Baytrail and need tuned for Quawks board
register "usb2_per_port_lane0" = "0x00049a09"
register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d"
register "usb2_per_port_lane1" = "0x00049a09"
@@ -74,7 +73,7 @@ chip soc/intel/baytrail
device pci 1a.0 off end # TXE
device pci 1b.0 on end # HDA
device pci 1c.0 on end # PCIE_PORT1
- device pci 1c.1 on end # PCIE_PORT2
+ device pci 1c.1 off end # PCIE_PORT2
device pci 1c.2 off end # PCIE_PORT3
device pci 1c.3 off end # PCIE_PORT4
device pci 1d.0 on end # EHCI
diff --git a/src/mainboard/google/rambi/variants/banjo/devicetree.cb b/src/mainboard/google/rambi/variants/banjo/devicetree.cb
deleted file mode 100644
index 55d9873fda..0000000000
--- a/src/mainboard/google/rambi/variants/banjo/devicetree.cb
+++ /dev/null
@@ -1,104 +0,0 @@
-chip soc/intel/baytrail
-
- # SATA port enable mask (2 ports)
- register "sata_port_map" = "0x1"
- register "sata_ahci" = "0x1"
- register "ide_legacy_combined" = "0x0"
-
- # Route USB ports to XHCI
- register "usb_route_to_xhci" = "1"
-
- # USB Port Disable Mask
- register "usb2_port_disable_mask" = "0x0"
- register "usb3_port_disable_mask" = "0x0"
-
- # USB PHY settings
- # TODO: These values are from Baytrail and need tuned for Banjo board
- register "usb2_per_port_lane0" = "0x00049a09"
- register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d"
- register "usb2_per_port_lane1" = "0x00049a09"
- register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d"
- register "usb2_per_port_lane2" = "0x00049209"
- register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015"
- register "usb2_per_port_lane3" = "0x00049a09"
- register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d"
-
- # LPE audio codec settings
- register "lpe_codec_clk_freq" = "25" # 25MHz clock
- register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0]
-
- # SD Card controller
- register "sdcard_cap_low" = "0x0"
- register "sdcard_cap_high" = "0x0"
-
- # Enable devices in ACPI mode
- register "lpe_acpi_mode" = "1"
- register "lpss_acpi_mode" = "1"
- register "scc_acpi_mode" = "1"
-
- # Allow PCIe devices to wake system from suspend
- register "pcie_wake_enable" = "1"
-
- # Enable PIPEA as DP_C
- register "gpu_pipea_port_select" = "2" # DP_C
- register "gpu_pipea_power_cycle_delay" = "6" # 600ms
- register "gpu_pipea_power_on_delay" = "5000" # 500ms
- register "gpu_pipea_light_on_delay" = "70" # 7ms
- register "gpu_pipea_power_off_delay" = "500" # 50ms
- register "gpu_pipea_light_off_delay" = "2000" # 200ms
-
- # VR PS2 control
- register "vnn_ps2_enable" = "1"
- register "vcc_ps2_enable" = "1"
-
- # Disable SLP_X stretching after SUS power well fail.
- register "disable_slp_x_stretch_sus_fail" = "1"
-
- device cpu_cluster 0 on
- device lapic 0 on end
- end
- device domain 0 on
- device pci 00.0 on end # SoC router
- device pci 02.0 on end # GFX
- device pci 11.0 off end # SDIO
- device pci 12.0 off end # SD
- device pci 13.0 on end # SATA
- device pci 14.0 on end # XHCI
- device pci 15.0 on end # LPE
- device pci 17.0 on end # MMC
- device pci 18.0 on end # SIO_DMA1
- device pci 18.1 on end # I2C1
- device pci 18.2 on end # I2C2
- device pci 18.3 off end # I2C3
- device pci 18.4 off end # I2C4
- device pci 18.5 off end # I2C5
- device pci 18.6 off end # I2C6
- device pci 18.7 off end # I2C7
- device pci 1a.0 off end # TXE
- device pci 1b.0 on end # HDA
- device pci 1c.0 on end # PCIE_PORT1
- device pci 1c.1 off end # PCIE_PORT2
- device pci 1c.2 off end # PCIE_PORT3
- device pci 1c.3 off end # PCIE_PORT4
- device pci 1d.0 on end # EHCI
- device pci 1e.0 on end # SIO_DMA2
- device pci 1e.1 off end # PWM1
- device pci 1e.2 off end # PWM2
- device pci 1e.3 off end # HSUART1
- device pci 1e.4 off end # HSUART2
- device pci 1e.5 off end # SPI
- device pci 1f.0 on
- chip drivers/pc80/tpm
- device pnp 0c31.0 on end
- end
- chip ec/google/chromeec
- # We only have one init function that
- # we need to call to initialize the
- # keyboard part of the EC.
- device pnp ff.1 on # dummy address
- end
- end
- end # LPC Bridge
- device pci 1f.3 off end # SMBus
- end
-end
diff --git a/src/mainboard/google/rambi/variants/banjo/overridetree.cb b/src/mainboard/google/rambi/variants/banjo/overridetree.cb
new file mode 100644
index 0000000000..bd37ec63bd
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/banjo/overridetree.cb
@@ -0,0 +1,11 @@
+chip soc/intel/baytrail
+
+ register "sdcard_cap_low" = "0x0"
+
+ # Allow PCIe devices to wake system from suspend
+ register "pcie_wake_enable" = "1"
+
+ device domain 0 on
+ device pci 12.0 off end # SD
+ end
+end
diff --git a/src/mainboard/google/rambi/variants/candy/devicetree.cb b/src/mainboard/google/rambi/variants/candy/devicetree.cb
deleted file mode 100644
index e048361b77..0000000000
--- a/src/mainboard/google/rambi/variants/candy/devicetree.cb
+++ /dev/null
@@ -1,105 +0,0 @@
-chip soc/intel/baytrail
-
- # SATA port enable mask (2 ports)
- register "sata_port_map" = "0x1"
- register "sata_ahci" = "0x1"
- register "ide_legacy_combined" = "0x0"
-
- # Route USB ports to XHCI
- register "usb_route_to_xhci" = "1"
-
- # USB Port Disable Mask
- register "usb2_port_disable_mask" = "0x0"
- register "usb3_port_disable_mask" = "0x0"
-
- # USB PHY settings
- # TODO: These values are from Baytrail and need tuned for Candy board
- register "usb2_per_port_lane0" = "0x00049a09"
- register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d"
- register "usb2_per_port_lane1" = "0x00049a09"
- register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d"
- register "usb2_per_port_lane2" = "0x00049209"
- register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015"
- register "usb2_per_port_lane3" = "0x00049a09"
- register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d"
- register "usb2_comp_bg" = "0x4700"
-
- # LPE audio codec settings
- register "lpe_codec_clk_freq" = "25" # 25MHz clock
- register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0]
-
- # SD Card controller
- register "sdcard_cap_low" = "0x036864b2"
- register "sdcard_cap_high" = "0x0"
-
- # Enable devices in ACPI mode
- register "lpe_acpi_mode" = "1"
- register "lpss_acpi_mode" = "1"
- register "scc_acpi_mode" = "1"
-
- # Allow PCIe devices to wake system from suspend
- register "pcie_wake_enable" = "1"
-
- # Enable PIPEA as DP_C
- register "gpu_pipea_port_select" = "2" # DP_C
- register "gpu_pipea_power_cycle_delay" = "6" # 600ms
- register "gpu_pipea_power_on_delay" = "5000" # 500ms
- register "gpu_pipea_light_on_delay" = "70" # 7ms
- register "gpu_pipea_power_off_delay" = "500" # 50ms
- register "gpu_pipea_light_off_delay" = "2000" # 200ms
-
- # VR PS2 control
- register "vnn_ps2_enable" = "1"
- register "vcc_ps2_enable" = "1"
-
- # Disable SLP_X stretching after SUS power well fail.
- register "disable_slp_x_stretch_sus_fail" = "1"
-
- device cpu_cluster 0 on
- device lapic 0 on end
- end
- device domain 0 on
- device pci 00.0 on end # SoC router
- device pci 02.0 on end # GFX
- device pci 11.0 off end # SDIO
- device pci 12.0 on end # SD
- device pci 13.0 on end # SATA
- device pci 14.0 on end # XHCI
- device pci 15.0 on end # LPE
- device pci 17.0 on end # MMC
- device pci 18.0 on end # SIO_DMA1
- device pci 18.1 on end # I2C1
- device pci 18.2 on end # I2C2
- device pci 18.3 off end # I2C3
- device pci 18.4 off end # I2C4
- device pci 18.5 off end # I2C5
- device pci 18.6 on end # I2C6
- device pci 18.7 off end # I2C7
- device pci 1a.0 off end # TXE
- device pci 1b.0 on end # HDA
- device pci 1c.0 on end # PCIE_PORT1
- device pci 1c.1 off end # PCIE_PORT2
- device pci 1c.2 off end # PCIE_PORT3
- device pci 1c.3 off end # PCIE_PORT4
- device pci 1d.0 on end # EHCI
- device pci 1e.0 on end # SIO_DMA2
- device pci 1e.1 off end # PWM1
- device pci 1e.2 off end # PWM2
- device pci 1e.3 off end # HSUART1
- device pci 1e.4 off end # HSUART2
- device pci 1e.5 off end # SPI
- device pci 1f.0 on
- chip drivers/pc80/tpm
- device pnp 0c31.0 on end
- end
- chip ec/google/chromeec
- # We only have one init function that
- # we need to call to initialize the
- # keyboard part of the EC.
- device pnp ff.1 on # dummy address
- end
- end
- end # LPC Bridge
- device pci 1f.3 off end # SMBus
- end
-end
diff --git a/src/mainboard/google/rambi/variants/candy/overridetree.cb b/src/mainboard/google/rambi/variants/candy/overridetree.cb
new file mode 100644
index 0000000000..dcd001b8ae
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/candy/overridetree.cb
@@ -0,0 +1,11 @@
+chip soc/intel/baytrail
+
+ register "usb2_comp_bg" = "0x4700"
+
+ # Allow PCIe devices to wake system from suspend
+ register "pcie_wake_enable" = "1"
+
+ device domain 0 on
+ device pci 18.6 on end # I2C6
+ end
+end
diff --git a/src/mainboard/google/rambi/variants/clapper/devicetree.cb b/src/mainboard/google/rambi/variants/clapper/devicetree.cb
deleted file mode 100644
index c010af1e73..0000000000
--- a/src/mainboard/google/rambi/variants/clapper/devicetree.cb
+++ /dev/null
@@ -1,101 +0,0 @@
-chip soc/intel/baytrail
-
- # SATA port enable mask (2 ports)
- register "sata_port_map" = "0x1"
- register "sata_ahci" = "0x1"
- register "ide_legacy_combined" = "0x0"
-
- # Route USB ports to XHCI
- register "usb_route_to_xhci" = "1"
-
- # USB Port Disable Mask
- register "usb2_port_disable_mask" = "0x0"
- register "usb3_port_disable_mask" = "0x0"
-
- # USB PHY settings
- # TODO: These values are from Baytrail and need tuned for Clapper board
- register "usb2_per_port_lane0" = "0x00049a09"
- register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d"
- register "usb2_per_port_lane1" = "0x00049a09"
- register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d"
- register "usb2_per_port_lane2" = "0x00049209"
- register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015"
- register "usb2_per_port_lane3" = "0x00049a09"
- register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d"
-
- # LPE audio codec settings
- register "lpe_codec_clk_freq" = "25" # 25MHz clock
- register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0]
-
- # SD Card controller
- register "sdcard_cap_low" = "0x036864b2"
- register "sdcard_cap_high" = "0x0"
-
- # Enable devices in ACPI mode
- register "lpe_acpi_mode" = "1"
- register "lpss_acpi_mode" = "1"
- register "scc_acpi_mode" = "1"
-
- # Enable PIPEA as DP_C
- register "gpu_pipea_port_select" = "2" # DP_C
- register "gpu_pipea_power_cycle_delay" = "6" # 600ms
- register "gpu_pipea_power_on_delay" = "5000" # 500ms
- register "gpu_pipea_light_on_delay" = "70" # 7ms
- register "gpu_pipea_power_off_delay" = "500" # 50ms
- register "gpu_pipea_light_off_delay" = "2000" # 200ms
-
- # VR PS2 control
- register "vnn_ps2_enable" = "1"
- register "vcc_ps2_enable" = "1"
-
- # Disable SLP_X stretching after SUS power well fail.
- register "disable_slp_x_stretch_sus_fail" = "1"
-
- device cpu_cluster 0 on
- device lapic 0 on end
- end
- device domain 0 on
- device pci 00.0 on end # SoC router
- device pci 02.0 on end # GFX
- device pci 11.0 off end # SDIO
- device pci 12.0 on end # SD
- device pci 13.0 on end # SATA
- device pci 14.0 on end # XHCI
- device pci 15.0 on end # LPE
- device pci 17.0 on end # MMC
- device pci 18.0 on end # SIO_DMA1
- device pci 18.1 on end # I2C1
- device pci 18.2 on end # I2C2
- device pci 18.3 off end # I2C3
- device pci 18.4 off end # I2C4
- device pci 18.5 on end # I2C5
- device pci 18.6 on end # I2C6
- device pci 18.7 off end # I2C7
- device pci 1a.0 off end # TXE
- device pci 1b.0 on end # HDA
- device pci 1c.0 on end # PCIE_PORT1
- device pci 1c.1 on end # PCIE_PORT2
- device pci 1c.2 off end # PCIE_PORT3
- device pci 1c.3 off end # PCIE_PORT4
- device pci 1d.0 on end # EHCI
- device pci 1e.0 on end # SIO_DMA2
- device pci 1e.1 off end # PWM1
- device pci 1e.2 off end # PWM2
- device pci 1e.3 off end # HSUART1
- device pci 1e.4 off end # HSUART2
- device pci 1e.5 off end # SPI
- device pci 1f.0 on
- chip drivers/pc80/tpm
- device pnp 0c31.0 on end
- end
- chip ec/google/chromeec
- # We only have one init function that
- # we need to call to initialize the
- # keyboard part of the EC.
- device pnp ff.1 on # dummy address
- end
- end
- end # LPC Bridge
- device pci 1f.3 off end # SMBus
- end
-end
diff --git a/src/mainboard/google/rambi/variants/clapper/overridetree.cb b/src/mainboard/google/rambi/variants/clapper/overridetree.cb
new file mode 100644
index 0000000000..ce81c2d48c
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/clapper/overridetree.cb
@@ -0,0 +1,8 @@
+chip soc/intel/baytrail
+
+ device domain 0 on
+ device pci 18.5 on end # I2C5
+ device pci 18.6 on end # I2C6
+ device pci 1c.1 on end # PCIE_PORT2
+ end
+end
diff --git a/src/mainboard/google/rambi/variants/enguarde/devicetree.cb b/src/mainboard/google/rambi/variants/enguarde/devicetree.cb
deleted file mode 100644
index 0db28d5edf..0000000000
--- a/src/mainboard/google/rambi/variants/enguarde/devicetree.cb
+++ /dev/null
@@ -1,104 +0,0 @@
-chip soc/intel/baytrail
-
- # SATA port enable mask (2 ports)
- register "sata_port_map" = "0x1"
- register "sata_ahci" = "0x1"
- register "ide_legacy_combined" = "0x0"
-
- # Route USB ports to XHCI
- register "usb_route_to_xhci" = "1"
-
- # USB Port Disable Mask
- register "usb2_port_disable_mask" = "0x0"
- register "usb3_port_disable_mask" = "0x0"
-
- # USB PHY settings
- # TODO: These values are from Baytrail and need tuned for Enguarde board
- register "usb2_per_port_lane0" = "0x00049a09"
- register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d"
- register "usb2_per_port_lane1" = "0x00049a09"
- register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d"
- register "usb2_per_port_lane2" = "0x00049209"
- register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015"
- register "usb2_per_port_lane3" = "0x00049a09"
- register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d"
-
- # LPE audio codec settings
- register "lpe_codec_clk_freq" = "25" # 25MHz clock
- register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0]
-
- # SD Card controller
- register "sdcard_cap_low" = "0x036864b2"
- register "sdcard_cap_high" = "0x0"
-
- # Enable devices in ACPI mode
- register "lpe_acpi_mode" = "1"
- register "lpss_acpi_mode" = "1"
- register "scc_acpi_mode" = "1"
-
- # Allow PCIe devices to wake system from suspend
- register "pcie_wake_enable" = "1"
-
- # Enable PIPEA as DP_C
- register "gpu_pipea_port_select" = "2" # DP_C
- register "gpu_pipea_power_cycle_delay" = "6" # 600ms
- register "gpu_pipea_power_on_delay" = "5000" # 500ms
- register "gpu_pipea_light_on_delay" = "70" # 7ms
- register "gpu_pipea_power_off_delay" = "500" # 50ms
- register "gpu_pipea_light_off_delay" = "2000" # 200ms
-
- # VR PS2 control
- register "vnn_ps2_enable" = "1"
- register "vcc_ps2_enable" = "1"
-
- # Disable SLP_X stretching after SUS power well fail.
- register "disable_slp_x_stretch_sus_fail" = "1"
-
- device cpu_cluster 0 on
- device lapic 0 on end
- end
- device domain 0 on
- device pci 00.0 on end # SoC router
- device pci 02.0 on end # GFX
- device pci 11.0 off end # SDIO
- device pci 12.0 on end # SD
- device pci 13.0 on end # SATA
- device pci 14.0 on end # XHCI
- device pci 15.0 on end # LPE
- device pci 17.0 on end # MMC
- device pci 18.0 on end # SIO_DMA1
- device pci 18.1 on end # I2C1
- device pci 18.2 on end # I2C2
- device pci 18.3 off end # I2C3
- device pci 18.4 off end # I2C4
- device pci 18.5 off end # I2C5
- device pci 18.6 off end # I2C6
- device pci 18.7 off end # I2C7
- device pci 1a.0 off end # TXE
- device pci 1b.0 on end # HDA
- device pci 1c.0 on end # PCIE_PORT1
- device pci 1c.1 on end # PCIE_PORT2
- device pci 1c.2 off end # PCIE_PORT3
- device pci 1c.3 off end # PCIE_PORT4
- device pci 1d.0 on end # EHCI
- device pci 1e.0 on end # SIO_DMA2
- device pci 1e.1 off end # PWM1
- device pci 1e.2 off end # PWM2
- device pci 1e.3 off end # HSUART1
- device pci 1e.4 off end # HSUART2
- device pci 1e.5 off end # SPI
- device pci 1f.0 on
- chip drivers/pc80/tpm
- device pnp 0c31.0 on end
- end
- chip ec/google/chromeec
- # We only have one init function that
- # we need to call to initialize the
- # keyboard part of the EC.
- device pnp ff.1 on # dummy address
- end
- end
- end # LPC Bridge
- device pci 1f.3 off end # SMBus
- end
-end
diff --git a/src/mainboard/google/rambi/variants/enguarde/overridetree.cb b/src/mainboard/google/rambi/variants/enguarde/overridetree.cb
new file mode 100644
index 0000000000..5a0589ac43
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/enguarde/overridetree.cb
@@ -0,0 +1,9 @@
+chip soc/intel/baytrail
+
+ # Allow PCIe devices to wake system from suspend
+ register "pcie_wake_enable" = "1"
+
+ device domain 0 on
+ device pci 1c.1 on end # PCIE_PORT2
+ end
+end
diff --git a/src/mainboard/google/rambi/variants/glimmer/devicetree.cb b/src/mainboard/google/rambi/variants/glimmer/devicetree.cb
deleted file mode 100644
index 5e7d6466dd..0000000000
--- a/src/mainboard/google/rambi/variants/glimmer/devicetree.cb
+++ /dev/null
@@ -1,101 +0,0 @@
-chip soc/intel/baytrail
-
- # SATA port enable mask (2 ports)
- register "sata_port_map" = "0x1"
- register "sata_ahci" = "0x1"
- register "ide_legacy_combined" = "0x0"
-
- # Route USB ports to XHCI
- register "usb_route_to_xhci" = "1"
-
- # USB Port Disable Mask
- register "usb2_port_disable_mask" = "0x0"
- register "usb3_port_disable_mask" = "0x0"
-
- # USB PHY settings
- # TODO: These values are from Baytrail and need tuned for Glimmer board
- register "usb2_per_port_lane0" = "0x00049a09"
- register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d"
- register "usb2_per_port_lane1" = "0x00049a09"
- register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d"
- register "usb2_per_port_lane2" = "0x00049209"
- register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015"
- register "usb2_per_port_lane3" = "0x00049a09"
- register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d"
-
- # LPE audio codec settings
- register "lpe_codec_clk_freq" = "25" # 25MHz clock
- register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0]
-
- # SD Card controller
- register "sdcard_cap_low" = "0x036864b2"
- register "sdcard_cap_high" = "0x0"
-
- # Enable devices in ACPI mode
- register "lpe_acpi_mode" = "1"
- register "lpss_acpi_mode" = "1"
- register "scc_acpi_mode" = "1"
-
- # Enable PIPEA as DP_C
- register "gpu_pipea_port_select" = "2" # DP_C
- register "gpu_pipea_power_cycle_delay" = "6" # 600ms
- register "gpu_pipea_power_on_delay" = "5000" # 500ms
- register "gpu_pipea_light_on_delay" = "70" # 7ms
- register "gpu_pipea_power_off_delay" = "500" # 50ms
- register "gpu_pipea_light_off_delay" = "2000" # 200ms
-
- # VR PS2 control
- register "vnn_ps2_enable" = "1"
- register "vcc_ps2_enable" = "1"
-
- # Disable SLP_X stretching after SUS power well fail.
- register "disable_slp_x_stretch_sus_fail" = "1"
-
- device cpu_cluster 0 on
- device lapic 0 on end
- end
- device domain 0 on
- device pci 00.0 on end # SoC router
- device pci 02.0 on end # GFX
- device pci 11.0 off end # SDIO
- device pci 12.0 on end # SD
- device pci 13.0 on end # SATA
- device pci 14.0 on end # XHCI
- device pci 15.0 on end # LPE
- device pci 17.0 on end # MMC
- device pci 18.0 on end # SIO_DMA1
- device pci 18.1 on end # I2C1
- device pci 18.2 on end # I2C2
- device pci 18.3 off end # I2C3
- device pci 18.4 off end # I2C4
- device pci 18.5 off end # I2C5
- device pci 18.6 on end # I2C6
- device pci 18.7 off end # I2C7
- device pci 1a.0 off end # TXE
- device pci 1b.0 on end # HDA
- device pci 1c.0 on end # PCIE_PORT1
- device pci 1c.1 on end # PCIE_PORT2
- device pci 1c.2 off end # PCIE_PORT3
- device pci 1c.3 off end # PCIE_PORT4
- device pci 1d.0 on end # EHCI
- device pci 1e.0 on end # SIO_DMA2
- device pci 1e.1 off end # PWM1
- device pci 1e.2 off end # PWM2
- device pci 1e.3 off end # HSUART1
- device pci 1e.4 off end # HSUART2
- device pci 1e.5 off end # SPI
- device pci 1f.0 on
- chip drivers/pc80/tpm
- device pnp 0c31.0 on end
- end
- chip ec/google/chromeec
- # We only have one init function that
- # we need to call to initialize the
- # keyboard part of the EC.
- device pnp ff.1 on # dummy address
- end
- end
- end # LPC Bridge
- device pci 1f.3 off end # SMBus
- end
-end
diff --git a/src/mainboard/google/rambi/variants/glimmer/overridetree.cb b/src/mainboard/google/rambi/variants/glimmer/overridetree.cb
new file mode 100644
index 0000000000..37b7c539b0
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/glimmer/overridetree.cb
@@ -0,0 +1,7 @@
+chip soc/intel/baytrail
+
+ device domain 0 on
+ device pci 18.6 on end # I2C6
+ device pci 1c.1 on end # PCIE_PORT2
+ end
+end
diff --git a/src/mainboard/google/rambi/variants/gnawty/devicetree.cb b/src/mainboard/google/rambi/variants/gnawty/devicetree.cb
deleted file mode 100644
index 3559d9941a..0000000000
--- a/src/mainboard/google/rambi/variants/gnawty/devicetree.cb
+++ /dev/null
@@ -1,104 +0,0 @@
-chip soc/intel/baytrail
-
- # SATA port enable mask (2 ports)
- register "sata_port_map" = "0x1"
- register "sata_ahci" = "0x1"
- register "ide_legacy_combined" = "0x0"
-
- # Route USB ports to XHCI
- register "usb_route_to_xhci" = "1"
-
- # USB Port Disable Mask
- register "usb2_port_disable_mask" = "0x0"
- register "usb3_port_disable_mask" = "0x0"
-
- # USB PHY settings
- # TODO: These values are from Baytrail and need tuned for Gnawty board
- register "usb2_per_port_lane0" = "0x00049a09"
- register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d"
- register "usb2_per_port_lane1" = "0x00049a09"
- register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d"
- register "usb2_per_port_lane2" = "0x00049209"
- register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015"
- register "usb2_per_port_lane3" = "0x00049a09"
- register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d"
-
- # LPE audio codec settings
- register "lpe_codec_clk_freq" = "25" # 25MHz clock
- register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0]
-
- # SD Card controller
- register "sdcard_cap_low" = "0x036864b2"
- register "sdcard_cap_high" = "0x0"
-
- # Enable devices in ACPI mode
- register "lpe_acpi_mode" = "1"
- register "lpss_acpi_mode" = "1"
- register "scc_acpi_mode" = "1"
-
- # Allow PCIe devices to wake system from suspend
- register "pcie_wake_enable" = "1"
-
- # Enable PIPEA as DP_C
- register "gpu_pipea_port_select" = "2" # DP_C
- register "gpu_pipea_power_cycle_delay" = "6" # 600ms
- register "gpu_pipea_power_on_delay" = "5000" # 500ms
- register "gpu_pipea_light_on_delay" = "70" # 7ms
- register "gpu_pipea_power_off_delay" = "500" # 50ms
- register "gpu_pipea_light_off_delay" = "2000" # 200ms
-
- # VR PS2 control
- register "vnn_ps2_enable" = "1"
- register "vcc_ps2_enable" = "1"
-
- # Disable SLP_X stretching after SUS power well fail.
- register "disable_slp_x_stretch_sus_fail" = "1"
-
- device cpu_cluster 0 on
- device lapic 0 on end
- end
- device domain 0 on
- device pci 00.0 on end # SoC router
- device pci 02.0 on end # GFX
- device pci 11.0 off end # SDIO
- device pci 12.0 on end # SD
- device pci 13.0 on end # SATA
- device pci 14.0 on end # XHCI
- device pci 15.0 on end # LPE
- device pci 17.0 on end # MMC
- device pci 18.0 on end # SIO_DMA1
- device pci 18.1 on end # I2C1
- device pci 18.2 on end # I2C2
- device pci 18.3 off end # I2C3
- device pci 18.4 off end # I2C4
- device pci 18.5 off end # I2C5
- device pci 18.6 off end # I2C6
- device pci 18.7 off end # I2C7
- device pci 1a.0 off end # TXE
- device pci 1b.0 on end # HDA
- device pci 1c.0 on end # PCIE_PORT1
- device pci 1c.1 on end # PCIE_PORT2
- device pci 1c.2 off end # PCIE_PORT3
- device pci 1c.3 off end # PCIE_PORT4
- device pci 1d.0 on end # EHCI
- device pci 1e.0 on end # SIO_DMA2
- device pci 1e.1 off end # PWM1
- device pci 1e.2 off end # PWM2
- device pci 1e.3 off end # HSUART1
- device pci 1e.4 off end # HSUART2
- device pci 1e.5 off end # SPI
- device pci 1f.0 on
- chip drivers/pc80/tpm
- device pnp 0c31.0 on end
- end
- chip ec/google/chromeec
- # We only have one init function that
- # we need to call to initialize the
- # keyboard part of the EC.
- device pnp ff.1 on # dummy address
- end
- end
- end # LPC Bridge
- device pci 1f.3 off end # SMBus
- end
-end
diff --git a/src/mainboard/google/rambi/variants/gnawty/overridetree.cb b/src/mainboard/google/rambi/variants/gnawty/overridetree.cb
new file mode 100644
index 0000000000..5a0589ac43
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/gnawty/overridetree.cb
@@ -0,0 +1,9 @@
+chip soc/intel/baytrail
+
+ # Allow PCIe devices to wake system from suspend
+ register "pcie_wake_enable" = "1"
+
+ device domain 0 on
+ device pci 1c.1 on end # PCIE_PORT2
+ end
+end
diff --git a/src/mainboard/google/rambi/variants/heli/devicetree.cb b/src/mainboard/google/rambi/variants/heli/devicetree.cb
deleted file mode 100644
index d6536c35a5..0000000000
--- a/src/mainboard/google/rambi/variants/heli/devicetree.cb
+++ /dev/null
@@ -1,105 +0,0 @@
-chip soc/intel/baytrail
-
- # SATA port enable mask (2 ports)
- register "sata_port_map" = "0x1"
- register "sata_ahci" = "0x1"
- register "ide_legacy_combined" = "0x0"
-
- # Route USB ports to XHCI
- register "usb_route_to_xhci" = "1"
-
- # USB Port Disable Mask
- register "usb2_port_disable_mask" = "0x0"
- register "usb3_port_disable_mask" = "0x0"
-
- # USB PHY settings
- # TODO: These values are from Baytrail and need tuned for Heli board
- register "usb2_per_port_lane0" = "0x00049a09"
- register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d"
- register "usb2_per_port_lane1" = "0x00049a09"
- register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d"
- register "usb2_per_port_lane2" = "0x00049209"
- register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015"
- register "usb2_per_port_lane3" = "0x00049a09"
- register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d"
- register "usb2_comp_bg" = "0x4700"
-
- # LPE audio codec settings
- register "lpe_codec_clk_freq" = "25" # 25MHz clock
- register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0]
-
- # SD Card controller
- register "sdcard_cap_low" = "0x036864b2"
- register "sdcard_cap_high" = "0x0"
-
- # Enable devices in ACPI mode
- register "lpe_acpi_mode" = "1"
- register "lpss_acpi_mode" = "1"
- register "scc_acpi_mode" = "1"
-
- # Allow PCIe devices to wake system from suspend
- register "pcie_wake_enable" = "1"
-
- # Enable PIPEA as DP_C
- register "gpu_pipea_port_select" = "2" # DP_C
- register "gpu_pipea_power_cycle_delay" = "6" # 600ms
- register "gpu_pipea_power_on_delay" = "5000" # 500ms
- register "gpu_pipea_light_on_delay" = "70" # 7ms
- register "gpu_pipea_power_off_delay" = "500" # 50ms
- register "gpu_pipea_light_off_delay" = "2000" # 200ms
-
- # VR PS2 control
- register "vnn_ps2_enable" = "1"
- register "vcc_ps2_enable" = "1"
-
- # Disable SLP_X stretching after SUS power well fail.
- register "disable_slp_x_stretch_sus_fail" = "1"
-
- device cpu_cluster 0 on
- device lapic 0 on end
- end
- device domain 0 on
- device pci 00.0 on end # SoC router
- device pci 02.0 on end # GFX
- device pci 11.0 off end # SDIO
- device pci 12.0 on end # SD
- device pci 13.0 on end # SATA
- device pci 14.0 on end # XHCI
- device pci 15.0 on end # LPE
- device pci 17.0 on end # MMC
- device pci 18.0 on end # SIO_DMA1
- device pci 18.1 on end # I2C1
- device pci 18.2 on end # I2C2
- device pci 18.3 off end # I2C3
- device pci 18.4 off end # I2C4
- device pci 18.5 off end # I2C5
- device pci 18.6 off end # I2C6
- device pci 18.7 off end # I2C7
- device pci 1a.0 off end # TXE
- device pci 1b.0 on end # HDA
- device pci 1c.0 on end # PCIE_PORT1
- device pci 1c.1 on end # PCIE_PORT2
- device pci 1c.2 off end # PCIE_PORT3
- device pci 1c.3 off end # PCIE_PORT4
- device pci 1d.0 on end # EHCI
- device pci 1e.0 on end # SIO_DMA2
- device pci 1e.1 off end # PWM1
- device pci 1e.2 off end # PWM2
- device pci 1e.3 off end # HSUART1
- device pci 1e.4 off end # HSUART2
- device pci 1e.5 off end # SPI
- device pci 1f.0 on
- chip drivers/pc80/tpm
- device pnp 0c31.0 on end
- end
- chip ec/google/chromeec
- # We only have one init function that
- # we need to call to initialize the
- # keyboard part of the EC.
- device pnp ff.1 on # dummy address
- end
- end
- end # LPC Bridge
- device pci 1f.3 off end # SMBus
- end
-end
diff --git a/src/mainboard/google/rambi/variants/heli/overridetree.cb b/src/mainboard/google/rambi/variants/heli/overridetree.cb
new file mode 100644
index 0000000000..fb59964b6a
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/heli/overridetree.cb
@@ -0,0 +1,11 @@
+chip soc/intel/baytrail
+
+ register "usb2_comp_bg" = "0x4700"
+
+ # Allow PCIe devices to wake system from suspend
+ register "pcie_wake_enable" = "1"
+
+ device domain 0 on
+ device pci 1c.1 on end # PCIE_PORT2
+ end
+end
diff --git a/src/mainboard/google/rambi/variants/kip/devicetree.cb b/src/mainboard/google/rambi/variants/kip/devicetree.cb
deleted file mode 100644
index 24facb300d..0000000000
--- a/src/mainboard/google/rambi/variants/kip/devicetree.cb
+++ /dev/null
@@ -1,104 +0,0 @@
-chip soc/intel/baytrail
-
- # SATA port enable mask (2 ports)
- register "sata_port_map" = "0x1"
- register "sata_ahci" = "0x1"
- register "ide_legacy_combined" = "0x0"
-
- # Route USB ports to XHCI
- register "usb_route_to_xhci" = "1"
-
- # USB Port Disable Mask
- register "usb2_port_disable_mask" = "0x0"
- register "usb3_port_disable_mask" = "0x0"
-
- # USB PHY settings
- # TODO: These values are from Baytrail and need tuned for Kip board
- register "usb2_per_port_lane0" = "0x00049a09"
- register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d"
- register "usb2_per_port_lane1" = "0x00049a09"
- register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d"
- register "usb2_per_port_lane2" = "0x00049209"
- register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015"
- register "usb2_per_port_lane3" = "0x00049a09"
- register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d"
-
- # LPE audio codec settings
- register "lpe_codec_clk_freq" = "25" # 25MHz clock
- register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0]
-
- # SD Card controller
- register "sdcard_cap_low" = "0x036864b2"
- register "sdcard_cap_high" = "0x0"
-
- # Enable devices in ACPI mode
- register "lpe_acpi_mode" = "1"
- register "lpss_acpi_mode" = "1"
- register "scc_acpi_mode" = "1"
-
- # Allow PCIe devices to wake system from suspend
- register "pcie_wake_enable" = "1"
-
- # Enable PIPEA as DP_C
- register "gpu_pipea_port_select" = "2" # DP_C
- register "gpu_pipea_power_cycle_delay" = "6" # 600ms
- register "gpu_pipea_power_on_delay" = "5000" # 500ms
- register "gpu_pipea_light_on_delay" = "70" # 7ms
- register "gpu_pipea_power_off_delay" = "500" # 50ms
- register "gpu_pipea_light_off_delay" = "2000" # 200ms
-
- # VR PS2 control
- register "vnn_ps2_enable" = "1"
- register "vcc_ps2_enable" = "1"
-
- # Disable SLP_X stretching after SUS power well fail.
- register "disable_slp_x_stretch_sus_fail" = "1"
-
- device cpu_cluster 0 on
- device lapic 0 on end
- end
- device domain 0 on
- device pci 00.0 on end # SoC router
- device pci 02.0 on end # GFX
- device pci 11.0 off end # SDIO
- device pci 12.0 on end # SD
- device pci 13.0 on end # SATA
- device pci 14.0 on end # XHCI
- device pci 15.0 on end # LPE
- device pci 17.0 on end # MMC
- device pci 18.0 on end # SIO_DMA1
- device pci 18.1 on end # I2C1
- device pci 18.2 on end # I2C2
- device pci 18.3 off end # I2C3
- device pci 18.4 off end # I2C4
- device pci 18.5 off end # I2C5
- device pci 18.6 off end # I2C6
- device pci 18.7 off end # I2C7
- device pci 1a.0 off end # TXE
- device pci 1b.0 on end # HDA
- device pci 1c.0 on end # PCIE_PORT1
- device pci 1c.1 on end # PCIE_PORT2
- device pci 1c.2 off end # PCIE_PORT3
- device pci 1c.3 off end # PCIE_PORT4
- device pci 1d.0 on end # EHCI
- device pci 1e.0 on end # SIO_DMA2
- device pci 1e.1 off end # PWM1
- device pci 1e.2 off end # PWM2
- device pci 1e.3 off end # HSUART1
- device pci 1e.4 off end # HSUART2
- device pci 1e.5 off end # SPI
- device pci 1f.0 on
- chip drivers/pc80/tpm
- device pnp 0c31.0 on end
- end
- chip ec/google/chromeec
- # We only have one init function that
- # we need to call to initialize the
- # keyboard part of the EC.
- device pnp ff.1 on # dummy address
- end
- end
- end # LPC Bridge
- device pci 1f.3 off end # SMBus
- end
-end
diff --git a/src/mainboard/google/rambi/variants/kip/overridetree.cb b/src/mainboard/google/rambi/variants/kip/overridetree.cb
new file mode 100644
index 0000000000..5a0589ac43
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/kip/overridetree.cb
@@ -0,0 +1,9 @@
+chip soc/intel/baytrail
+
+ # Allow PCIe devices to wake system from suspend
+ register "pcie_wake_enable" = "1"
+
+ device domain 0 on
+ device pci 1c.1 on end # PCIE_PORT2
+ end
+end
diff --git a/src/mainboard/google/rambi/variants/ninja/devicetree.cb b/src/mainboard/google/rambi/variants/ninja/devicetree.cb
deleted file mode 100644
index b9e09e07ab..0000000000
--- a/src/mainboard/google/rambi/variants/ninja/devicetree.cb
+++ /dev/null
@@ -1,105 +0,0 @@
-chip soc/intel/baytrail
-
- # SATA port enable mask (2 ports)
- register "sata_port_map" = "0x1"
- register "sata_ahci" = "0x1"
- register "ide_legacy_combined" = "0x0"
-
- # Route USB ports to XHCI
- register "usb_route_to_xhci" = "1"
-
- # USB Port Disable Mask
- register "usb2_port_disable_mask" = "0x0"
- register "usb3_port_disable_mask" = "0x0"
-
- # USB PHY settings
- # TODO: These values are from Baytrail and need tuned for Ninja board
- register "usb2_per_port_lane0" = "0x00049a09"
- register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d"
- register "usb2_per_port_lane1" = "0x00049a09"
- register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d"
- register "usb2_per_port_lane2" = "0x00049209"
- register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015"
- register "usb2_per_port_lane3" = "0x00049a09"
- register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d"
- register "usb2_comp_bg" = "0x4700"
-
- # LPE audio codec settings
- register "lpe_codec_clk_freq" = "25" # 25MHz clock
- register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0]
-
- # SD Card controller
- register "sdcard_cap_low" = "0x036864b2"
- register "sdcard_cap_high" = "0x0"
-
- # Enable devices in ACPI mode
- register "lpe_acpi_mode" = "1"
- register "lpss_acpi_mode" = "1"
- register "scc_acpi_mode" = "1"
-
- # Allow PCIe devices to wake system from suspend
- register "pcie_wake_enable" = "1"
-
- # Enable PIPEA as DP_C
- register "gpu_pipea_port_select" = "2" # DP_C
- register "gpu_pipea_power_cycle_delay" = "6" # 600ms
- register "gpu_pipea_power_on_delay" = "5000" # 500ms
- register "gpu_pipea_light_on_delay" = "70" # 7ms
- register "gpu_pipea_power_off_delay" = "500" # 50ms
- register "gpu_pipea_light_off_delay" = "2000" # 200ms
-
- # VR PS2 control
- register "vnn_ps2_enable" = "1"
- register "vcc_ps2_enable" = "1"
-
- # Disable SLP_X stretching after SUS power well fail.
- register "disable_slp_x_stretch_sus_fail" = "1"
-
- device cpu_cluster 0 on
- device lapic 0 on end
- end
- device domain 0 on
- device pci 00.0 on end # SoC router
- device pci 02.0 on end # GFX
- device pci 11.0 off end # SDIO
- device pci 12.0 on end # SD
- device pci 13.0 on end # SATA
- device pci 14.0 on end # XHCI
- device pci 15.0 on end # LPE
- device pci 17.0 on end # MMC
- device pci 18.0 on end # SIO_DMA1
- device pci 18.1 on end # I2C1
- device pci 18.2 on end # I2C2
- device pci 18.3 off end # I2C3
- device pci 18.4 off end # I2C4
- device pci 18.5 off end # I2C5
- device pci 18.6 off end # I2C6
- device pci 18.7 off end # I2C7
- device pci 1a.0 off end # TXE
- device pci 1b.0 on end # HDA
- device pci 1c.0 on end # PCIE_PORT1
- device pci 1c.1 off end # PCIE_PORT2
- device pci 1c.2 on end # PCIE_PORT3
- device pci 1c.3 on end # PCIE_PORT4
- device pci 1d.0 on end # EHCI
- device pci 1e.0 on end # SIO_DMA2
- device pci 1e.1 off end # PWM1
- device pci 1e.2 off end # PWM2
- device pci 1e.3 off end # HSUART1
- device pci 1e.4 off end # HSUART2
- device pci 1e.5 off end # SPI
- device pci 1f.0 on
- chip drivers/pc80/tpm
- device pnp 0c31.0 on end
- end
- chip ec/google/chromeec
- # We only have one init function that
- # we need to call to initialize the
- # keyboard part of the EC.
- device pnp ff.1 on # dummy address
- end
- end
- end # LPC Bridge
- device pci 1f.3 off end # SMBus
- end
-end
diff --git a/src/mainboard/google/rambi/variants/ninja/overridetree.cb b/src/mainboard/google/rambi/variants/ninja/overridetree.cb
new file mode 100644
index 0000000000..3f67644d79
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/ninja/overridetree.cb
@@ -0,0 +1,12 @@
+chip soc/intel/baytrail
+
+ register "usb2_comp_bg" = "0x4700"
+
+ # Allow PCIe devices to wake system from suspend
+ register "pcie_wake_enable" = "1"
+
+ device domain 0 on
+ device pci 1c.2 on end # PCIE_PORT3
+ device pci 1c.3 on end # PCIE_PORT4
+ end
+end
diff --git a/src/mainboard/google/rambi/variants/orco/devicetree.cb b/src/mainboard/google/rambi/variants/orco/devicetree.cb
deleted file mode 100644
index c6123367f4..0000000000
--- a/src/mainboard/google/rambi/variants/orco/devicetree.cb
+++ /dev/null
@@ -1,104 +0,0 @@
-chip soc/intel/baytrail
-
- # SATA port enable mask (2 ports)
- register "sata_port_map" = "0x1"
- register "sata_ahci" = "0x1"
- register "ide_legacy_combined" = "0x0"
-
- # Route USB ports to XHCI
- register "usb_route_to_xhci" = "1"
-
- # USB Port Disable Mask
- register "usb2_port_disable_mask" = "0x0"
- register "usb3_port_disable_mask" = "0x0"
-
- # USB PHY settings
- # TODO: These values are from Baytrail and need tuned for Orco board
- register "usb2_per_port_lane0" = "0x00049a09"
- register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d"
- register "usb2_per_port_lane1" = "0x00049a09"
- register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d"
- register "usb2_per_port_lane2" = "0x00049209"
- register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015"
- register "usb2_per_port_lane3" = "0x00049a09"
- register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d"
-
- # LPE audio codec settings
- register "lpe_codec_clk_freq" = "25" # 25MHz clock
- register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0]
-
- # SD Card controller
- register "sdcard_cap_low" = "0x036864b2"
- register "sdcard_cap_high" = "0x0"
-
- # Enable devices in ACPI mode
- register "lpe_acpi_mode" = "1"
- register "lpss_acpi_mode" = "1"
- register "scc_acpi_mode" = "1"
-
- # Allow PCIe devices to wake system from suspend
- register "pcie_wake_enable" = "1"
-
- # Enable PIPEA as DP_C
- register "gpu_pipea_port_select" = "2" # DP_C
- register "gpu_pipea_power_cycle_delay" = "6" # 600ms
- register "gpu_pipea_power_on_delay" = "5000" # 500ms
- register "gpu_pipea_light_on_delay" = "70" # 7ms
- register "gpu_pipea_power_off_delay" = "500" # 50ms
- register "gpu_pipea_light_off_delay" = "2000" # 200ms
-
- # VR PS2 control
- register "vnn_ps2_enable" = "1"
- register "vcc_ps2_enable" = "1"
-
- # Disable SLP_X stretching after SUS power well fail.
- register "disable_slp_x_stretch_sus_fail" = "1"
-
- device cpu_cluster 0 on
- device lapic 0 on end
- end
- device domain 0 on
- device pci 00.0 on end # SoC router
- device pci 02.0 on end # GFX
- device pci 11.0 off end # SDIO
- device pci 12.0 on end # SD
- device pci 13.0 on end # SATA
- device pci 14.0 on end # XHCI
- device pci 15.0 on end # LPE
- device pci 17.0 on end # MMC
- device pci 18.0 on end # SIO_DMA1
- device pci 18.1 on end # I2C1
- device pci 18.2 on end # I2C2
- device pci 18.3 off end # I2C3
- device pci 18.4 off end # I2C4
- device pci 18.5 off end # I2C5
- device pci 18.6 off end # I2C6
- device pci 18.7 off end # I2C7
- device pci 1a.0 off end # TXE
- device pci 1b.0 on end # HDA
- device pci 1c.0 on end # PCIE_PORT1
- device pci 1c.1 on end # PCIE_PORT2
- device pci 1c.2 off end # PCIE_PORT3
- device pci 1c.3 off end # PCIE_PORT4
- device pci 1d.0 on end # EHCI
- device pci 1e.0 on end # SIO_DMA2
- device pci 1e.1 off end # PWM1
- device pci 1e.2 off end # PWM2
- device pci 1e.3 off end # HSUART1
- device pci 1e.4 off end # HSUART2
- device pci 1e.5 off end # SPI
- device pci 1f.0 on
- chip drivers/pc80/tpm
- device pnp 0c31.0 on end
- end
- chip ec/google/chromeec
- # We only have one init function that
- # we need to call to initialize the
- # keyboard part of the EC.
- device pnp ff.1 on # dummy address
- end
- end
- end # LPC Bridge
- device pci 1f.3 off end # SMBus
- end
-end
diff --git a/src/mainboard/google/rambi/variants/orco/overridetree.cb b/src/mainboard/google/rambi/variants/orco/overridetree.cb
new file mode 100644
index 0000000000..5a0589ac43
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/orco/overridetree.cb
@@ -0,0 +1,9 @@
+chip soc/intel/baytrail
+
+ # Allow PCIe devices to wake system from suspend
+ register "pcie_wake_enable" = "1"
+
+ device domain 0 on
+ device pci 1c.1 on end # PCIE_PORT2
+ end
+end
diff --git a/src/mainboard/google/rambi/variants/quawks/overridetree.cb b/src/mainboard/google/rambi/variants/quawks/overridetree.cb
new file mode 100644
index 0000000000..76bcf92a21
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/quawks/overridetree.cb
@@ -0,0 +1,6 @@
+chip soc/intel/baytrail
+
+ device domain 0 on
+ device pci 1c.1 on end # PCIE_PORT2
+ end
+end
diff --git a/src/mainboard/google/rambi/variants/rambi/devicetree.cb b/src/mainboard/google/rambi/variants/rambi/devicetree.cb
deleted file mode 100644
index 0fb7f14930..0000000000
--- a/src/mainboard/google/rambi/variants/rambi/devicetree.cb
+++ /dev/null
@@ -1,105 +0,0 @@
-chip soc/intel/baytrail
-
- # SATA port enable mask (2 ports)
- register "sata_port_map" = "0x1"
- register "sata_ahci" = "0x1"
- register "ide_legacy_combined" = "0x0"
-
- # Route USB ports to XHCI
- register "usb_route_to_xhci" = "1"
-
- # USB Port Disable Mask
- register "usb2_port_disable_mask" = "0x0"
- register "usb3_port_disable_mask" = "0x0"
-
- # USB PHY settings
- # TODO: These values are from Baytrail and need tuned for Rambi board
- register "usb2_per_port_lane0" = "0x00049a09"
- register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d"
- register "usb2_per_port_lane1" = "0x00049a09"
- register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d"
- register "usb2_per_port_lane2" = "0x00049209"
- register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015"
- register "usb2_per_port_lane3" = "0x00049a09"
- register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d"
- register "usb2_comp_bg" = "0x4700"
-
- # LPE audio codec settings
- register "lpe_codec_clk_freq" = "25" # 25MHz clock
- register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0]
-
- # SD Card controller
- register "sdcard_cap_low" = "0x036864b2"
- register "sdcard_cap_high" = "0x0"
-
- # Enable devices in ACPI mode
- register "lpe_acpi_mode" = "1"
- register "lpss_acpi_mode" = "1"
- register "scc_acpi_mode" = "1"
-
- # Allow PCIe devices to wake system from suspend
- register "pcie_wake_enable" = "1"
-
- # Enable PIPEA as DP_C
- register "gpu_pipea_port_select" = "2" # DP_C
- register "gpu_pipea_power_cycle_delay" = "6" # 600ms
- register "gpu_pipea_power_on_delay" = "5000" # 500ms
- register "gpu_pipea_light_on_delay" = "70" # 7ms
- register "gpu_pipea_power_off_delay" = "500" # 50ms
- register "gpu_pipea_light_off_delay" = "2000" # 200ms
-
- # VR PS2 control
- register "vnn_ps2_enable" = "1"
- register "vcc_ps2_enable" = "1"
-
- # Disable SLP_X stretching after SUS power well fail.
- register "disable_slp_x_stretch_sus_fail" = "1"
-
- device cpu_cluster 0 on
- device lapic 0 on end
- end
- device domain 0 on
- device pci 00.0 on end # SoC router
- device pci 02.0 on end # GFX
- device pci 11.0 off end # SDIO
- device pci 12.0 on end # SD
- device pci 13.0 on end # SATA
- device pci 14.0 on end # XHCI
- device pci 15.0 on end # LPE
- device pci 17.0 on end # MMC
- device pci 18.0 on end # SIO_DMA1
- device pci 18.1 on end # I2C1
- device pci 18.2 on end # I2C2
- device pci 18.3 off end # I2C3
- device pci 18.4 off end # I2C4
- device pci 18.5 off end # I2C5
- device pci 18.6 on end # I2C6
- device pci 18.7 off end # I2C7
- device pci 1a.0 off end # TXE
- device pci 1b.0 on end # HDA
- device pci 1c.0 on end # PCIE_PORT1
- device pci 1c.1 on end # PCIE_PORT2
- device pci 1c.2 off end # PCIE_PORT3
- device pci 1c.3 off end # PCIE_PORT4
- device pci 1d.0 on end # EHCI
- device pci 1e.0 on end # SIO_DMA2
- device pci 1e.1 off end # PWM1
- device pci 1e.2 off end # PWM2
- device pci 1e.3 off end # HSUART1
- device pci 1e.4 off end # HSUART2
- device pci 1e.5 off end # SPI
- device pci 1f.0 on
- chip drivers/pc80/tpm
- device pnp 0c31.0 on end
- end
- chip ec/google/chromeec
- # We only have one init function that
- # we need to call to initialize the
- # keyboard part of the EC.
- device pnp ff.1 on # dummy address
- end
- end
- end # LPC Bridge
- device pci 1f.3 off end # SMBus
- end
-end
diff --git a/src/mainboard/google/rambi/variants/rambi/overridetree.cb b/src/mainboard/google/rambi/variants/rambi/overridetree.cb
new file mode 100644
index 0000000000..7ba9463447
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/rambi/overridetree.cb
@@ -0,0 +1,12 @@
+chip soc/intel/baytrail
+
+ register "usb2_comp_bg" = "0x4700"
+
+ # Allow PCIe devices to wake system from suspend
+ register "pcie_wake_enable" = "1"
+
+ device domain 0 on
+ device pci 18.6 on end # I2C6
+ device pci 1c.1 on end # PCIE_PORT2
+ end
+end
diff --git a/src/mainboard/google/rambi/variants/squawks/devicetree.cb b/src/mainboard/google/rambi/variants/squawks/devicetree.cb
deleted file mode 100644
index 4ed27be478..0000000000
--- a/src/mainboard/google/rambi/variants/squawks/devicetree.cb
+++ /dev/null
@@ -1,101 +0,0 @@
-chip soc/intel/baytrail
-
- # SATA port enable mask (2 ports)
- register "sata_port_map" = "0x1"
- register "sata_ahci" = "0x1"
- register "ide_legacy_combined" = "0x0"
-
- # Route USB ports to XHCI
- register "usb_route_to_xhci" = "1"
-
- # USB Port Disable Mask
- register "usb2_port_disable_mask" = "0x0"
- register "usb3_port_disable_mask" = "0x0"
-
- # USB PHY settings
- # TODO: These values are from Baytrail and need tuned for Squawks board
- register "usb2_per_port_lane0" = "0x00049a09"
- register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d"
- register "usb2_per_port_lane1" = "0x00049a09"
- register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d"
- register "usb2_per_port_lane2" = "0x00049209"
- register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015"
- register "usb2_per_port_lane3" = "0x00049a09"
- register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d"
-
- # LPE audio codec settings
- register "lpe_codec_clk_freq" = "25" # 25MHz clock
- register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0]
-
- # SD Card controller
- register "sdcard_cap_low" = "0x036864b2"
- register "sdcard_cap_high" = "0x0"
-
- # Enable devices in ACPI mode
- register "lpe_acpi_mode" = "1"
- register "lpss_acpi_mode" = "1"
- register "scc_acpi_mode" = "1"
-
- # Enable PIPEA as DP_C
- register "gpu_pipea_port_select" = "2" # DP_C
- register "gpu_pipea_power_cycle_delay" = "6" # 600ms
- register "gpu_pipea_power_on_delay" = "5000" # 500ms
- register "gpu_pipea_light_on_delay" = "70" # 7ms
- register "gpu_pipea_power_off_delay" = "500" # 50ms
- register "gpu_pipea_light_off_delay" = "2000" # 200ms
-
- # VR PS2 control
- register "vnn_ps2_enable" = "1"
- register "vcc_ps2_enable" = "1"
-
- # Disable SLP_X stretching after SUS power well fail.
- register "disable_slp_x_stretch_sus_fail" = "1"
-
- device cpu_cluster 0 on
- device lapic 0 on end
- end
- device domain 0 on
- device pci 00.0 on end # SoC router
- device pci 02.0 on end # GFX
- device pci 11.0 off end # SDIO
- device pci 12.0 on end # SD
- device pci 13.0 on end # SATA
- device pci 14.0 on end # XHCI
- device pci 15.0 on end # LPE
- device pci 17.0 on end # MMC
- device pci 18.0 on end # SIO_DMA1
- device pci 18.1 on end # I2C1
- device pci 18.2 on end # I2C2
- device pci 18.3 off end # I2C3
- device pci 18.4 off end # I2C4
- device pci 18.5 off end # I2C5
- device pci 18.6 off end # I2C6
- device pci 18.7 off end # I2C7
- device pci 1a.0 off end # TXE
- device pci 1b.0 on end # HDA
- device pci 1c.0 on end # PCIE_PORT1
- device pci 1c.1 on end # PCIE_PORT2
- device pci 1c.2 off end # PCIE_PORT3
- device pci 1c.3 off end # PCIE_PORT4
- device pci 1d.0 on end # EHCI
- device pci 1e.0 on end # SIO_DMA2
- device pci 1e.1 off end # PWM1
- device pci 1e.2 off end # PWM2
- device pci 1e.3 off end # HSUART1
- device pci 1e.4 off end # HSUART2
- device pci 1e.5 off end # SPI
- device pci 1f.0 on
- chip drivers/pc80/tpm
- device pnp 0c31.0 on end
- end
- chip ec/google/chromeec
- # We only have one init function that
- # we need to call to initialize the
- # keyboard part of the EC.
- device pnp ff.1 on # dummy address
- end
- end
- end # LPC Bridge
- device pci 1f.3 off end # SMBus
- end
-end
diff --git a/src/mainboard/google/rambi/variants/squawks/overridetree.cb b/src/mainboard/google/rambi/variants/squawks/overridetree.cb
new file mode 100644
index 0000000000..76bcf92a21
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/squawks/overridetree.cb
@@ -0,0 +1,6 @@
+chip soc/intel/baytrail
+
+ device domain 0 on
+ device pci 1c.1 on end # PCIE_PORT2
+ end
+end
diff --git a/src/mainboard/google/rambi/variants/sumo/devicetree.cb b/src/mainboard/google/rambi/variants/sumo/devicetree.cb
deleted file mode 100644
index 8f093c61e5..0000000000
--- a/src/mainboard/google/rambi/variants/sumo/devicetree.cb
+++ /dev/null
@@ -1,105 +0,0 @@
-chip soc/intel/baytrail
-
- # SATA port enable mask (2 ports)
- register "sata_port_map" = "0x1"
- register "sata_ahci" = "0x1"
- register "ide_legacy_combined" = "0x0"
-
- # Route USB ports to XHCI
- register "usb_route_to_xhci" = "1"
-
- # USB Port Disable Mask
- register "usb2_port_disable_mask" = "0x0"
- register "usb3_port_disable_mask" = "0x0"
-
- # USB PHY settings
- # TODO: These values are from Baytrail and need tuned for Sumo board
- register "usb2_per_port_lane0" = "0x00049a09"
- register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d"
- register "usb2_per_port_lane1" = "0x00049a09"
- register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d"
- register "usb2_per_port_lane2" = "0x00049209"
- register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015"
- register "usb2_per_port_lane3" = "0x00049a09"
- register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d"
- register "usb2_comp_bg" = "0x4700"
-
- # LPE audio codec settings
- register "lpe_codec_clk_freq" = "25" # 25MHz clock
- register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0]
-
- # SD Card controller
- register "sdcard_cap_low" = "0x036864b2"
- register "sdcard_cap_high" = "0x0"
-
- # Enable devices in ACPI mode
- register "lpe_acpi_mode" = "1"
- register "lpss_acpi_mode" = "1"
- register "scc_acpi_mode" = "1"
-
- # Allow PCIe devices to wake system from suspend
- register "pcie_wake_enable" = "1"
-
- # Enable PIPEA as DP_C
- register "gpu_pipea_port_select" = "2" # DP_C
- register "gpu_pipea_power_cycle_delay" = "6" # 600ms
- register "gpu_pipea_power_on_delay" = "5000" # 500ms
- register "gpu_pipea_light_on_delay" = "70" # 7ms
- register "gpu_pipea_power_off_delay" = "500" # 50ms
- register "gpu_pipea_light_off_delay" = "2000" # 200ms
-
- # VR PS2 control
- register "vnn_ps2_enable" = "1"
- register "vcc_ps2_enable" = "1"
-
- # Disable SLP_X stretching after SUS power well fail.
- register "disable_slp_x_stretch_sus_fail" = "1"
-
- device cpu_cluster 0 on
- device lapic 0 on end
- end
- device domain 0 on
- device pci 00.0 on end # SoC router
- device pci 02.0 on end # GFX
- device pci 11.0 off end # SDIO
- device pci 12.0 on end # SD
- device pci 13.0 on end # SATA
- device pci 14.0 on end # XHCI
- device pci 15.0 on end # LPE
- device pci 17.0 on end # MMC
- device pci 18.0 on end # SIO_DMA1
- device pci 18.1 on end # I2C1
- device pci 18.2 on end # I2C2
- device pci 18.3 off end # I2C3
- device pci 18.4 off end # I2C4
- device pci 18.5 off end # I2C5
- device pci 18.6 on end # I2C6
- device pci 18.7 off end # I2C7
- device pci 1a.0 off end # TXE
- device pci 1b.0 on end # HDA
- device pci 1c.0 on end # PCIE_PORT1
- device pci 1c.1 off end # PCIE_PORT2
- device pci 1c.2 on end # PCIE_PORT3
- device pci 1c.3 on end # PCIE_PORT4
- device pci 1d.0 on end # EHCI
- device pci 1e.0 on end # SIO_DMA2
- device pci 1e.1 off end # PWM1
- device pci 1e.2 off end # PWM2
- device pci 1e.3 off end # HSUART1
- device pci 1e.4 off end # HSUART2
- device pci 1e.5 off end # SPI
- device pci 1f.0 on
- chip drivers/pc80/tpm
- device pnp 0c31.0 on end
- end
- chip ec/google/chromeec
- # We only have one init function that
- # we need to call to initialize the
- # keyboard part of the EC.
- device pnp ff.1 on # dummy address
- end
- end
- end # LPC Bridge
- device pci 1f.3 off end # SMBus
- end
-end
diff --git a/src/mainboard/google/rambi/variants/sumo/overridetree.cb b/src/mainboard/google/rambi/variants/sumo/overridetree.cb
new file mode 100644
index 0000000000..35052dc154
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/sumo/overridetree.cb
@@ -0,0 +1,13 @@
+chip soc/intel/baytrail
+
+ register "usb2_comp_bg" = "0x4700"
+
+ # Allow PCIe devices to wake system from suspend
+ register "pcie_wake_enable" = "1"
+
+ device domain 0 on
+ device pci 18.6 on end # I2C6
+ device pci 1c.2 on end # PCIE_PORT3
+ device pci 1c.3 on end # PCIE_PORT4
+ end
+end
diff --git a/src/mainboard/google/rambi/variants/swanky/devicetree.cb b/src/mainboard/google/rambi/variants/swanky/devicetree.cb
deleted file mode 100644
index 57f89109f3..0000000000
--- a/src/mainboard/google/rambi/variants/swanky/devicetree.cb
+++ /dev/null
@@ -1,104 +0,0 @@
-chip soc/intel/baytrail
-
- # SATA port enable mask (2 ports)
- register "sata_port_map" = "0x1"
- register "sata_ahci" = "0x1"
- register "ide_legacy_combined" = "0x0"
-
- # Route USB ports to XHCI
- register "usb_route_to_xhci" = "1"
-
- # USB Port Disable Mask
- register "usb2_port_disable_mask" = "0x0"
- register "usb3_port_disable_mask" = "0x0"
-
- # USB PHY settings
- # TODO: These values are from Baytrail and need tuned for Swanky board
- register "usb2_per_port_lane0" = "0x00049a09"
- register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d"
- register "usb2_per_port_lane1" = "0x00049a09"
- register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d"
- register "usb2_per_port_lane2" = "0x00049209"
- register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015"
- register "usb2_per_port_lane3" = "0x00049a09"
- register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d"
-
- # LPE audio codec settings
- register "lpe_codec_clk_freq" = "25" # 25MHz clock
- register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0]
-
- # SD Card controller
- register "sdcard_cap_low" = "0x036864b2"
- register "sdcard_cap_high" = "0x0"
-
- # Enable devices in ACPI mode
- register "lpe_acpi_mode" = "1"
- register "lpss_acpi_mode" = "1"
- register "scc_acpi_mode" = "1"
-
- # Allow PCIe devices to wake system from suspend
- register "pcie_wake_enable" = "1"
-
- # Enable PIPEA as DP_C
- register "gpu_pipea_port_select" = "2" # DP_C
- register "gpu_pipea_power_cycle_delay" = "6" # 600ms
- register "gpu_pipea_power_on_delay" = "5000" # 500ms
- register "gpu_pipea_light_on_delay" = "70" # 7ms
- register "gpu_pipea_power_off_delay" = "500" # 50ms
- register "gpu_pipea_light_off_delay" = "2000" # 200ms
-
- # VR PS2 control
- register "vnn_ps2_enable" = "1"
- register "vcc_ps2_enable" = "1"
-
- # Disable SLP_X stretching after SUS power well fail.
- register "disable_slp_x_stretch_sus_fail" = "1"
-
- device cpu_cluster 0 on
- device lapic 0 on end
- end
- device domain 0 on
- device pci 00.0 on end # SoC router
- device pci 02.0 on end # GFX
- device pci 11.0 off end # SDIO
- device pci 12.0 on end # SD
- device pci 13.0 on end # SATA
- device pci 14.0 on end # XHCI
- device pci 15.0 on end # LPE
- device pci 17.0 on end # MMC
- device pci 18.0 on end # SIO_DMA1
- device pci 18.1 on end # I2C1
- device pci 18.2 on end # I2C2
- device pci 18.3 off end # I2C3
- device pci 18.4 off end # I2C4
- device pci 18.5 off end # I2C5
- device pci 18.6 off end # I2C6
- device pci 18.7 off end # I2C7
- device pci 1a.0 off end # TXE
- device pci 1b.0 on end # HDA
- device pci 1c.0 on end # PCIE_PORT1
- device pci 1c.1 on end # PCIE_PORT2
- device pci 1c.2 off end # PCIE_PORT3
- device pci 1c.3 off end # PCIE_PORT4
- device pci 1d.0 on end # EHCI
- device pci 1e.0 on end # SIO_DMA2
- device pci 1e.1 off end # PWM1
- device pci 1e.2 off end # PWM2
- device pci 1e.3 off end # HSUART1
- device pci 1e.4 off end # HSUART2
- device pci 1e.5 off end # SPI
- device pci 1f.0 on
- chip drivers/pc80/tpm
- device pnp 0c31.0 on end
- end
- chip ec/google/chromeec
- # We only have one init function that
- # we need to call to initialize the
- # keyboard part of the EC.
- device pnp ff.1 on # dummy address
- end
- end
- end # LPC Bridge
- device pci 1f.3 off end # SMBus
- end
-end
diff --git a/src/mainboard/google/rambi/variants/swanky/overridetree.cb b/src/mainboard/google/rambi/variants/swanky/overridetree.cb
new file mode 100644
index 0000000000..5a0589ac43
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/swanky/overridetree.cb
@@ -0,0 +1,9 @@
+chip soc/intel/baytrail
+
+ # Allow PCIe devices to wake system from suspend
+ register "pcie_wake_enable" = "1"
+
+ device domain 0 on
+ device pci 1c.1 on end # PCIE_PORT2
+ end
+end
diff --git a/src/mainboard/google/rambi/variants/winky/devicetree.cb b/src/mainboard/google/rambi/variants/winky/devicetree.cb
deleted file mode 100644
index ed582ad21b..0000000000
--- a/src/mainboard/google/rambi/variants/winky/devicetree.cb
+++ /dev/null
@@ -1,105 +0,0 @@
-chip soc/intel/baytrail
-
- # SATA port enable mask (2 ports)
- register "sata_port_map" = "0x1"
- register "sata_ahci" = "0x1"
- register "ide_legacy_combined" = "0x0"
-
- # Route USB ports to XHCI
- register "usb_route_to_xhci" = "1"
-
- # USB Port Disable Mask
- register "usb2_port_disable_mask" = "0x0"
- register "usb3_port_disable_mask" = "0x0"
-
- # USB PHY settings
- # TODO: These values are from Baytrail and need tuned for Winky board
- register "usb2_comp_bg" = "0x4680"
- register "usb2_per_port_lane0" = "0x0004C209"
- register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d"
- register "usb2_per_port_lane1" = "0x00049a09"
- register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d"
- register "usb2_per_port_lane2" = "0x00049209"
- register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015"
- register "usb2_per_port_lane3" = "0x0004B209"
- register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d"
-
- # LPE audio codec settings
- register "lpe_codec_clk_freq" = "25" # 25MHz clock
- register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0]
-
- # SD Card controller
- register "sdcard_cap_low" = "0x036864b2"
- register "sdcard_cap_high" = "0x0"
-
- # Enable devices in ACPI mode
- register "lpe_acpi_mode" = "1"
- register "lpss_acpi_mode" = "1"
- register "scc_acpi_mode" = "1"
-
- # Allow PCIe devices to wake system from suspend
- register "pcie_wake_enable" = "1"
-
- # Enable PIPEA as DP_C
- register "gpu_pipea_port_select" = "2" # DP_C
- register "gpu_pipea_power_cycle_delay" = "6" # 600ms
- register "gpu_pipea_power_on_delay" = "5000" # 500ms
- register "gpu_pipea_light_on_delay" = "70" # 7ms
- register "gpu_pipea_power_off_delay" = "500" # 50ms
- register "gpu_pipea_light_off_delay" = "2000" # 200ms
-
- # VR PS2 control
- register "vnn_ps2_enable" = "1"
- register "vcc_ps2_enable" = "1"
-
- # Disable SLP_X stretching after SUS power well fail.
- register "disable_slp_x_stretch_sus_fail" = "1"
-
- device cpu_cluster 0 on
- device lapic 0 on end
- end
- device domain 0 on
- device pci 00.0 on end # SoC router
- device pci 02.0 on end # GFX
- device pci 11.0 off end # SDIO
- device pci 12.0 on end # SD
- device pci 13.0 on end # SATA
- device pci 14.0 on end # XHCI
- device pci 15.0 on end # LPE
- device pci 17.0 on end # MMC
- device pci 18.0 on end # SIO_DMA1
- device pci 18.1 on end # I2C1
- device pci 18.2 on end # I2C2
- device pci 18.3 off end # I2C3
- device pci 18.4 off end # I2C4
- device pci 18.5 off end # I2C5
- device pci 18.6 off end # I2C6
- device pci 18.7 off end # I2C7
- device pci 1a.0 off end # TXE
- device pci 1b.0 on end # HDA
- device pci 1c.0 on end # PCIE_PORT1
- device pci 1c.1 on end # PCIE_PORT2
- device pci 1c.2 off end # PCIE_PORT3
- device pci 1c.3 off end # PCIE_PORT4
- device pci 1d.0 on end # EHCI
- device pci 1e.0 on end # SIO_DMA2
- device pci 1e.1 off end # PWM1
- device pci 1e.2 off end # PWM2
- device pci 1e.3 off end # HSUART1
- device pci 1e.4 off end # HSUART2
- device pci 1e.5 off end # SPI
- device pci 1f.0 on
- chip drivers/pc80/tpm
- device pnp 0c31.0 on end
- end
- chip ec/google/chromeec
- # We only have one init function that
- # we need to call to initialize the
- # keyboard part of the EC.
- device pnp ff.1 on # dummy address
- end
- end
- end # LPC Bridge
- device pci 1f.3 off end # SMBus
- end
-end
diff --git a/src/mainboard/google/rambi/variants/winky/overridetree.cb b/src/mainboard/google/rambi/variants/winky/overridetree.cb
new file mode 100644
index 0000000000..d09ecbc48d
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/winky/overridetree.cb
@@ -0,0 +1,13 @@
+chip soc/intel/baytrail
+
+ register "usb2_per_port_lane0" = "0x0004C209"
+ register "usb2_per_port_lane3" = "0x0004B209"
+ register "usb2_comp_bg" = "0x4680"
+
+ # Allow PCIe devices to wake system from suspend
+ register "pcie_wake_enable" = "1"
+
+ device domain 0 on
+ device pci 1c.1 on end # PCIE_PORT2
+ end
+end