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authorFurquan Shaikh <furquan@google.com>2020-06-02 22:38:53 -0700
committerPatrick Georgi <pgeorgi@google.com>2020-06-06 09:29:54 +0000
commit20ecf2268b13a4d2a8b4a8490139ee064d9d8f62 (patch)
tree4b4534d02db966263755d2902b63a215fffed9ba
parent4a93ba9f778f8927f2ad7bec7c8009640708560d (diff)
downloadcoreboot-20ecf2268b13a4d2a8b4a8490139ee064d9d8f62.tar.xz
lp4x: Add new memory parts and generate SPDs
This change adds the following memory parts to LP4x global list and generates SPDs using gen_spd.go for TGL and JSL: 1. MT53E512M32D2NP-046 WT:E 2. K4U6E3S4AA-MGCR 3. H9HCNNNCPMMLXR-NEE 4. K4UBE3D4AA-MGCR BUG=b:157862308, b:157732528 Change-Id: Ib7538247d39dfe5faab277d646f87f09103d6969 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41989 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/soc/intel/jasperlake/spd/lp4x/spd_manifest.generated.txt4
-rw-r--r--src/soc/intel/tigerlake/spd/lp4x/spd_manifest.generated.txt4
-rw-r--r--util/spd_tools/intel/lp4x/global_lp4x_mem_parts.json.txt50
3 files changed, 57 insertions, 1 deletions
diff --git a/src/soc/intel/jasperlake/spd/lp4x/spd_manifest.generated.txt b/src/soc/intel/jasperlake/spd/lp4x/spd_manifest.generated.txt
index e916733f43..564322e9e5 100644
--- a/src/soc/intel/jasperlake/spd/lp4x/spd_manifest.generated.txt
+++ b/src/soc/intel/jasperlake/spd/lp4x/spd_manifest.generated.txt
@@ -7,3 +7,7 @@ H9HKNNNCRMBVAR-NEH,spd-5.hex
MT53E1G64D4SQ-046 WT:A,spd-6.hex
MT53E512M32D2NP-046 WT:F,spd-1.hex
NT6AP256T32AV-J2,spd-7.hex
+K4U6E3S4AA-MGCR,spd-1.hex
+MT53E512M32D2NP-046 WT:E,spd-1.hex
+H9HCNNNCPMMLXR-NEE,spd-3.hex
+K4UBE3D4AA-MGCR,spd-3.hex
diff --git a/src/soc/intel/tigerlake/spd/lp4x/spd_manifest.generated.txt b/src/soc/intel/tigerlake/spd/lp4x/spd_manifest.generated.txt
index d11e93dbde..49fe4454e4 100644
--- a/src/soc/intel/tigerlake/spd/lp4x/spd_manifest.generated.txt
+++ b/src/soc/intel/tigerlake/spd/lp4x/spd_manifest.generated.txt
@@ -7,3 +7,7 @@ H9HKNNNCRMBVAR-NEH,spd-1.hex
MT53E1G64D4SQ-046 WT:A,spd-4.hex
MT53E512M32D2NP-046 WT:F,spd-1.hex
NT6AP256T32AV-J2,spd-5.hex
+K4U6E3S4AA-MGCR,spd-1.hex
+MT53E512M32D2NP-046 WT:E,spd-1.hex
+H9HCNNNCPMMLXR-NEE,spd-3.hex
+K4UBE3D4AA-MGCR,spd-3.hex
diff --git a/util/spd_tools/intel/lp4x/global_lp4x_mem_parts.json.txt b/util/spd_tools/intel/lp4x/global_lp4x_mem_parts.json.txt
index 5635158a79..b9dd4b3157 100644
--- a/util/spd_tools/intel/lp4x/global_lp4x_mem_parts.json.txt
+++ b/util/spd_tools/intel/lp4x/global_lp4x_mem_parts.json.txt
@@ -109,6 +109,54 @@
"tckMaxPs": 1250,
"casLatencies": "14 20 24 28 32"
}
- }
+ },
+ {
+ "name": "K4U6E3S4AA-MGCR",
+ "attribs": {
+ "densityPerChannelGb": 8,
+ "banks": 8,
+ "channelsPerDie": 2,
+ "diesPerPackage": 1,
+ "bitWidthPerChannel": 16,
+ "ranksPerChannel": 1,
+ "speedMbps": 4267
+ }
+ },
+ {
+ "name": "MT53E512M32D2NP-046 WT:E",
+ "attribs": {
+ "densityPerChannelGb": 8,
+ "banks": 8,
+ "channelsPerDie": 2,
+ "diesPerPackage": 1,
+ "bitWidthPerChannel": 16,
+ "ranksPerChannel": 1,
+ "speedMbps": 4267
+ }
+ },
+ {
+ "name": "H9HCNNNCPMMLXR-NEE",
+ "attribs": {
+ "densityPerChannelGb": 8,
+ "banks": 8,
+ "channelsPerDie": 2,
+ "diesPerPackage": 2,
+ "bitWidthPerChannel": 16,
+ "ranksPerChannel": 2,
+ "speedMbps": 4267
+ }
+ },
+ {
+ "name": "K4UBE3D4AA-MGCR",
+ "attribs": {
+ "densityPerChannelGb": 8,
+ "banks": 8,
+ "channelsPerDie": 2,
+ "diesPerPackage": 2,
+ "bitWidthPerChannel": 16,
+ "ranksPerChannel": 2,
+ "speedMbps": 4267
+ }
+ }
]
}