diff options
| author | Bora Guvendik <bora.guvendik@intel.com> | 2016-08-16 14:43:16 -0700 |
|---|---|---|
| committer | Andrey Petrov <andrey.petrov@intel.com> | 2016-08-18 20:17:41 +0200 |
| commit | 240853bf25cbff39f0099dd6ed3fe0bfa75c9d0c (patch) | |
| tree | 67aaabd7e796bb75db3c38c7c0e8f09de7979172 | |
| parent | 3ad63565a54f5ea3cdd866cbc6c70c67ad2757fe (diff) | |
| download | coreboot-240853bf25cbff39f0099dd6ed3fe0bfa75c9d0c.tar.xz | |
intel/amenia: Update eMMC DLL settings
Update eMMC DLL setting for amenia board, after that system can
boot up with eMMC successfully.
BUG=chrome-os-partner:51844
TEST=Boot up with eMMC
Change-Id: Ia7bd96db69fbe575e57847249c34d91b2a1fdcef
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/16237
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
| -rw-r--r-- | src/mainboard/intel/amenia/devicetree.cb | 22 |
1 files changed, 21 insertions, 1 deletions
diff --git a/src/mainboard/intel/amenia/devicetree.cb b/src/mainboard/intel/amenia/devicetree.cb index 4b620a04bc..0e47d2ec2a 100644 --- a/src/mainboard/intel/amenia/devicetree.cb +++ b/src/mainboard/intel/amenia/devicetree.cb @@ -7,11 +7,31 @@ chip soc/intel/apollolake register "pcie_rp0_clkreq_pin" = "3" # wifi/bt register "pcie_rp2_clkreq_pin" = "0" # SSD - # EMMC TX DATA Delay 1# + # eMMC TX DATA Delay 1# # 0x1A[14:8] stands for 26*125 = 3250 pSec delay for HS400 # 0x1A[6:0] stands for 26*125 = 3250 pSec delay for SDR104/HS200 register "emmc_tx_data_cntl1" = "0x1A1A" # HS400 required + # eMMC TX DATA Delay 2# + # 0x1C[30:24] stands for 28*125 = 3500 pSec delay for SDR50 + # 0x1C[22:16] stands for 28*125 = 3500 pSec delay for DDR50 + # 0x1C[14:8] stands for 28*125 = 3500 pSec delay for SDR25/HS50 + # 0x00[6:0] stands for 0 delay for SDR12/Compatibility mode + register "emmc_tx_data_cntl2" = "0x1c1c1c00" + + # eMMC RX CMD/DATA Delay 1# + # 0x1C[30:24] stands for 28*125 = 3500 pSec delay for SDR50 + # 0x1C[22:16] stands for 28*125 = 3500 pSec delay for DDR50 + # 0x1C[14:8] stands for 28*125 = 3500 pSec delay for SDR25/HS50 + # 0x00[6:0] stands for 0 delay for SDR12/Compatibility + register "emmc_rx_cmd_data_cntl1" = "0x1c1c1c00" + + # eMMC RX CMD/DATA Delay 2# + # 0x01[17:16] stands for Rx Clock before Output Buffer + # 0x00[14:8] stands for 0 delay for Auto Tuning Mode + # 0x1C[6:0] stands for 28*125 = 3500 pSec delay for SDR104/HS200 + register "emmc_rx_cmd_data_cntl2" = "0x1001c" + # LPSS S0ix Enable register "lpss_s0ix_enable" = "1" |