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| author | Jonathan Neuschäfer <j.neuschaefer@gmx.net> | 2018-02-13 14:01:22 +0100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-02-20 20:44:53 +0000 |
| commit | 2764919dfb78127517dcf13c6ec002f937626b02 (patch) | |
| tree | b52b33e34058215ec4df0227888b33010d38e06a | |
| parent | 27d34022588717dd5e5f9c309d362b645c2a9ffa (diff) | |
| download | coreboot-2764919dfb78127517dcf13c6ec002f937626b02.tar.xz | |
arch/riscv: Make RVC support configurable
In order to support RISC-V processors with and without the RVC
extension, configure the architecture variant (-march=...) explicitly.
NOTE: Spike does support RVC, but currently doesn't select
ARCH_RISCV_COMPRESSED, because coreboot's trap handler doesn't
support RVC.
Change-Id: Id4f69fa6b33604a5aa60fd6f6da8bd966494112f
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
| -rw-r--r-- | src/arch/riscv/Kconfig | 7 | ||||
| -rw-r--r-- | src/arch/riscv/Makefile.inc | 16 |
2 files changed, 20 insertions, 3 deletions
diff --git a/src/arch/riscv/Kconfig b/src/arch/riscv/Kconfig index a30cb7091b..2513c50030 100644 --- a/src/arch/riscv/Kconfig +++ b/src/arch/riscv/Kconfig @@ -2,6 +2,13 @@ config ARCH_RISCV bool default n +config ARCH_RISCV_COMPRESSED + bool + default n + help + Enable this option if your RISC-V processor supports compressed + instructions (RVC). Currently, this enables RVC for all stages. + config ARCH_BOOTBLOCK_RISCV bool default n diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index d2b6cce11d..4b2ff035d7 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -15,14 +15,24 @@ ## ################################################################################ -riscv_flags = -I$(src)/arch/riscv/ -mcmodel=medany - -riscv_asm_flags = +################################################################################ +## RISC-V specific options +################################################################################ ifeq ($(CONFIG_ARCH_RAMSTAGE_RISCV),y) check-ramstage-overlap-regions += stack endif +riscv_arch = rv64imafd + +ifeq ($(CONFIG_ARCH_RISCV_COMPRESSED),y) + riscv_arch := $(riscv_arch)c +endif + +riscv_flags = -I$(src)/arch/riscv/ -mcmodel=medany -march=$(riscv_arch) + +riscv_asm_flags = -march=$(riscv_arch) + ################################################################################ ## bootblock ################################################################################ |