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authorStefan Reinauer <stepan@coreboot.org>2010-12-11 22:12:32 +0000
committerStefan Reinauer <stepan@openbios.org>2010-12-11 22:12:32 +0000
commit2b9070a610132eaf61dca67e7713c082903fffef (patch)
tree0fcb1995cd569975914c94725c8da5f66ad524ed
parente7a30ee1663ebce8cfec3c2fb21eee8e1c1246a2 (diff)
downloadcoreboot-2b9070a610132eaf61dca67e7713c082903fffef.tar.xz
catch some illegal configurations (trivial)
Signed-off-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6163 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
-rw-r--r--src/northbridge/intel/i945/raminit.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index 77b9ade6c4..7e2cf81d28 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -541,6 +541,8 @@ static void sdram_detect_cas_latency_and_ram_speed(struct sys_info * sysinfo, u8
highest_supported_cas = 4;
} else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_3) {
highest_supported_cas = 3;
+ } else {
+ die("Invalid max. CAS.\n");
}
if (current_cas_mask & SPD_CAS_LATENCY_DDR2_3) {
current_cas = 3;
@@ -548,6 +550,8 @@ static void sdram_detect_cas_latency_and_ram_speed(struct sys_info * sysinfo, u8
current_cas = 4;
} else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_5) {
current_cas = 5;
+ } else {
+ die("Invalid CAS.\n");
}
idx = highest_supported_cas - current_cas;