Add ASUS DSBF mainboard

Change-Id: Iad38b92ca3a582e5aec07b92c994bfbe78b09855
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1223
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

9 files changed, 641 insertions, 1 deletions

diff --git a/src/mainboard/asus/Kconfig b/src/mainboard/asus/Kconfig
index f7a30174a9..1ca127834d 100644
--- a/src/mainboard/asus/Kconfig
+++ b/src/mainboard/asus/Kconfig
@@ -59,7 +59,8 @@ config BOARD_ASUS_P2B_LS
 	bool "P2B-LS"
 config BOARD_ASUS_P3B_F
 	bool "P3B-F"
-
+config BOARD_ASUS_DSBF
+	bool "DSBF"
 endchoice
 
 source "src/mainboard/asus/a8n_e/Kconfig"
@@ -81,6 +82,7 @@ source "src/mainboard/asus/p2b-ds/Kconfig"
 source "src/mainboard/asus/p2b-f/Kconfig"
 source "src/mainboard/asus/p2b-ls/Kconfig"
 source "src/mainboard/asus/p3b-f/Kconfig"
+source "src/mainboard/asus/dsbf/Kconfig
 
 config MAINBOARD_VENDOR
 	string
diff --git a/src/mainboard/asus/dsbf/Kconfig b/src/mainboard/asus/dsbf/Kconfig
new file mode 100644
index 0000000000..436ef0cf49
--- /dev/null
+++ b/src/mainboard/asus/dsbf/Kconfig
@@ -0,0 +1,45 @@
+if BOARD_ASUS_DSBF
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select ARCH_X86
+	select CPU_INTEL_SOCKET_LGA771
+	select SOUTHBRIDGE_INTEL_I3100
+	select NORTHBRIDGE_INTEL_I5000
+	select SUPERIO_WINBOND_W83627HF
+	select MMCONF_SUPPORT
+	select BOARD_ROMSIZE_KB_512
+	select HAVE_MP_TABLE
+	select HAVE_PIRQ_TABLE
+	select DRIVERS_I2C_W83793
+	select DRIVERS_GENERIC_IOAPIC
+
+config MAINBOARD_DIR
+	string
+	default asus/dsbf
+
+config DCACHE_RAM_BASE
+	hex
+	default 0xffdf8000
+
+config DCACHE_RAM_SIZE
+	hex
+	default 0x8000
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "DSBF"
+
+config MMCONF_BASE_ADDRESS
+	hex
+	default 0xe0000000
+
+config IRQ_SLOT_COUNT
+	int
+	default 48
+
+config MAX_CPUS
+	int
+	default 8
+
+endif
diff --git a/src/mainboard/asus/dsbf/chip.h b/src/mainboard/asus/dsbf/chip.h
new file mode 100644
index 0000000000..70f9bb43a6
--- /dev/null
+++ b/src/mainboard/asus/dsbf/chip.h
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2011 Sven Schnelle <svens@stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+extern struct chip_operations mainboard_ops;
+struct mainboard_config {};
diff --git a/src/mainboard/asus/dsbf/cmos.layout b/src/mainboard/asus/dsbf/cmos.layout
new file mode 100644
index 0000000000..29e78ad883
--- /dev/null
+++ b/src/mainboard/asus/dsbf/cmos.layout
@@ -0,0 +1,142 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2007-2008 coresystems GmbH
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; version 2 of
+# the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+# -----------------------------------------------------------------
+entries
+
+#start-bit length  config config-ID    name
+#0            8       r       0        seconds
+#8            8       r       0        alarm_seconds
+#16           8       r       0        minutes
+#24           8       r       0        alarm_minutes
+#32           8       r       0        hours
+#40           8       r       0        alarm_hours
+#48           8       r       0        day_of_week
+#56           8       r       0        day_of_month
+#64           8       r       0        month
+#72           8       r       0        year
+# -----------------------------------------------------------------
+# Status Register A
+#80           4       r       0        rate_select
+#84           3       r       0        REF_Clock
+#87           1       r       0        UIP
+# -----------------------------------------------------------------
+# Status Register B
+#88           1       r       0        auto_switch_DST
+#89           1       r       0        24_hour_mode
+#90           1       r       0        binary_values_enable
+#91           1       r       0        square-wave_out_enable
+#92           1       r       0        update_finished_enable
+#93           1       r       0        alarm_interrupt_enable
+#94           1       r       0        periodic_interrupt_enable
+#95           1       r       0        disable_clock_updates
+# -----------------------------------------------------------------
+# Status Register C
+#96           4       r       0        status_c_rsvd
+#100          1       r       0        uf_flag
+#101          1       r       0        af_flag
+#102          1       r       0        pf_flag
+#103          1       r       0        irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104          7       r       0        status_d_rsvd
+#111          1       r       0        valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112          8       r       0        diag_rsvd1
+
+# -----------------------------------------------------------------
+0          120       r       0        reserved_memory
+#120        264       r       0        unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384          1       e       4        boot_option
+385          1       e       4        last_boot
+388          4       r       0        reboot_bits
+#390          2       r       0        unused?
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+392          3       e       5        baud_rate
+395          4       e       6        debug_level
+#399          1       r       0        unused
+
+# coreboot config options: cpu
+400          1       e       2        hyper_threading
+#401          7       r       0        unused
+
+# coreboot config options: southbridge
+408          1       e       1        nmi
+#409          2       e       7        power_on_after_fail
+#411          5       r       0        unused
+
+# coreboot config options: bootloader
+416        512       s       0        boot_devices
+928          8       h       0        boot_default
+936          1       e       8        cmos_defaults_loaded
+937          1       e       1        lpt
+#938         46       r       0        unused
+
+# coreboot config options: check sums
+984         16       h       0        check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+5     0     115200
+5     1     57600
+5     2     38400
+5     3     19200
+5     4     9600
+5     5     4800
+5     6     2400
+5     7     1200
+6     1     Emergency
+6     2     Alert
+6     3     Critical
+6     4     Error
+6     5     Warning
+6     6     Notice
+6     7     Info
+6     8     Debug
+6     9     Spew
+7     0     Disable
+7     1     Enable
+7     2     Keep
+8     0     No
+8     1     Yes
+9     0	    Secondary
+9     1	    Primary
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 983 984
+
+
diff --git a/src/mainboard/asus/dsbf/devicetree.cb b/src/mainboard/asus/dsbf/devicetree.cb
new file mode 100644
index 0000000000..b18fdaf302
--- /dev/null
+++ b/src/mainboard/asus/dsbf/devicetree.cb
@@ -0,0 +1,185 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2009 coresystems GmbH
+## Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
+##
+## This program is free software; you can redistribute it and/or
+## modify it under the terms of the GNU General Public License as
+## published by the Free Software Foundation; version 2 of
+## the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+## MA 02110-1301 USA
+##
+
+chip northbridge/intel/i5000
+
+	device lapic_cluster 0 on
+		chip cpu/intel/socket_LGA771
+			device lapic 0 on end
+		end
+	end
+
+	device pci_domain 0 on
+		device pci 00.0 on # Host bridge
+			subsystemid 0x1043 0x81db
+		end
+
+		device pci 02.0 on # PCI Express x8 Port 2-3
+			ioapic_irq 8 INTA 0x10
+			ioapic_irq 8 INTB 0x11
+			ioapic_irq 8 INTC 0x12
+			ioapic_irq 8 INTD 0x13
+			device pci 00.0 on # PCI Express Upstream Port
+				device pci 00.0 on # PCI Express Downstream Port E1
+					device pci 00.0 on # 6700PXH PCI Express-to-PCI Bridge A
+					       ioapic_irq 8 INTA 0x11
+					       ioapic_irq 8 INTB 0x10
+					       ioapic_irq 8 INTC 0x11
+					       ioapic_irq 8 INTD 0x10
+						# PCI slot
+						device pci 00.2 on # 6700PXH PCI Express-to-PCI Bridge B
+							# PCI slot
+						end
+					end
+				end
+				device pci 00.1 on end
+				device pci 00.3 on # PCI Express to PCI-X Bridge
+					ioapic_irq 9 INTA 3
+					ioapic_irq 9 INTB 0
+					ioapic_irq 9 INTC 1
+					ioapic_irq 9 INTD 2
+					   # PCI-X Slot
+				end
+
+			end
+		end
+
+		device pci 03.0 on
+		       ioapic_irq 8 INTA 0x10
+		end
+		device pci 04.0 on
+		       ioapic_irq 8 INTA 0x10
+		end
+		device pci 05.0 on
+		       ioapic_irq 8 INTA 0x10
+		end
+		device pci 06.0 on
+		       ioapic_irq 8 INTA 0x10
+		end
+		device pci 07.0 on
+		       ioapic_irq 8 INTA 0x10
+		end
+
+		device pci 10.0 on end # FBD
+		device pci 10.1 on end # FBD
+		device pci 10.2 on end # FBD
+		device pci 11.0 on end # FBD reserved
+		device pci 13.0 on end # FBD reserved
+		device pci 15.0 on end # FBD
+		device pci 16.0 on end # FBD
+
+		chip drivers/generic/ioapic
+		     register "have_isa_interrupts" = "1"
+		     register "irq_on_fsb" = "1"
+		     register "enable_virtual_wire" = "1"
+		     register "base" = "0xfec00000"
+		     device ioapic 8 on end
+		end
+
+		chip drivers/generic/ioapic
+		     register "irq_on_fsb" = "1"
+		     register "base" = "0xfec80000"
+		     device ioapic 9 on end
+		end
+
+		chip southbridge/intel/i3100
+			register "pirq_a_d" = "0x0b0b0b0b"
+			register "pirq_e_h" = "0x80808080"
+			register "sata_ports_implemented" = "0x3f"
+
+			device pci 1c.0 on
+				ioapic_irq 8 INTA 0x14
+				ioapic_irq 8 INTB 0x15
+				ioapic_irq 8 INTC 0x16
+				ioapic_irq 8 INTD 0x17
+			end # PCIe bridge
+			device pci 1d.0 on
+				ioapic_irq 8 INTA 0x10
+			end # USB UHCI
+			device pci 1d.1 on
+				ioapic_irq 8 INTB 0x11
+			end # USB UHCI
+			device pci 1d.2 on
+				ioapic_irq 8 INTC 0x12
+			end # USB UHCI
+			device pci 1d.3 on
+				ioapic_irq 8 INTD 0x13
+			end # USB UHCI
+			device pci 1d.7 on end # USB2 EHCI
+			device pci 1e.0 on
+				device pci 01.0 on end
+			end
+
+			device pci 1f.0 on # PCI-LPC bridge
+				ioapic_irq 8 INTA 0x11
+				chip superio/winbond/w83627hf
+					device pnp 2e.0 off end # FDC
+					device pnp 2e.1 on # Parallel Port
+						io 0x60 = 0x378
+						irq 0x70 = 7
+					end
+					device pnp 2e.2 on # Serial Port 1
+						io 0x60 = 0x3f8
+						irq 0x70 = 4
+					end
+
+					device pnp 2e.3 off end
+					device pnp 2e.5 on # KBC
+					       io 0x60 = 0x60
+					       io 0x62 = 0x64
+					       irq 0x70 = 1
+					       irq 0x72 = 12
+					end
+
+					device pnp 2e.6 off end # CIR
+					device pnp 2e.7 off end # Game port / MIDI
+					device pnp 2e.8 off end # GPIO2
+					device pnp 2e.9 on end # GPIO3
+					device pnp 2e.a on end # ACPI
+					device pnp 2e.b off end # HWMON
+				end
+			end
+			device pci 1f.1 off end # IDE
+			device pci 1f.2 on end # SATA
+			device pci 1f.3 on # SMBUS
+				chip drivers/i2c/w83793
+					register "mfc" = "0x28"
+					register "fanin" = "0x1f"
+					register "peci_agent_conf" = "0x33"
+					register "tcase0" = "0x5e"
+					register "tcase1" = "0x5e"
+					register "tcase2" = "0x5e"
+					register "tcase3" = "0x5e"
+					register "tr_enable" = "0x01"
+					register "critical_temperature" = "0x7f"
+					register "td1_fan_select" = "0x09"
+					register "td2_fan_select" = "0x09"
+					register "td3_fan_select" = "0x09"
+					register "td4_fan_select" = "0x09"
+					register "tr1_fan_select" = "0x09"
+					register "tr2_fan_select" = "0x09"
+					device i2c 0x2f on end
+				end
+			end
+		end
+	end
+end
diff --git a/src/mainboard/asus/dsbf/irq_tables.c b/src/mainboard/asus/dsbf/irq_tables.c
new file mode 100644
index 0000000000..84f456a758
--- /dev/null
+++ b/src/mainboard/asus/dsbf/irq_tables.c
@@ -0,0 +1,57 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 Thomas Jourdan <thomas.jourdan@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/pirq_routing.h>
+
+const struct irq_routing_table intel_irq_routing_table = {
+	PIRQ_SIGNATURE,		/* u32 signature */
+	PIRQ_VERSION,		/* u16 version */
+	32 + 16 * CONFIG_IRQ_SLOT_COUNT,		/* Max. number of devices on the bus */
+	0x00,			/* Interrupt router bus */
+	(0x1f << 3) | 0x0,	/* Interrupt router dev */
+	0,			/* IRQs devoted exclusively to PCI usage */
+	0x8086,			/* Vendor */
+	0x2670,			/* Device */
+	0,			/* Miniport */
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+	0,			/* Checksum (has to be set to some value that
+				 * would give 0 after the sum of all bytes
+				 * for this structure (including checksum).
+                                 */
+	{
+		/* bus,        dev | fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+		{0x00, (0x1c << 3) | 0x0, {{0x60, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0},
+		{0x00, (0x1c << 3) | 0x1, {{0x00, 0x0000}, {0x61, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0},
+		{0x00, (0x1c << 3) | 0x2, {{0x00, 0x0000}, {0x00, 0x0000}, {0x62, 0x1ef8}, {0x00, 0x0000}}, 0, 0},
+		{0x00, (0x1c << 3) | 0x3, {{0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}, {0x63, 0x1ef8}}, 0, 0},
+		{0x00, (0x1d << 3) | 0x0, {{0x60, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0},
+		{0x00, (0x1d << 3) | 0x1, {{0x00, 0x0000}, {0x61, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0},
+		{0x00, (0x1d << 3) | 0x2, {{0x00, 0x0000}, {0x00, 0x0000}, {0x62, 0x1ef8}, {0x00, 0x0000}}, 0, 0},
+		{0x00, (0x1d << 3) | 0x3, {{0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}, {0x63, 0x1ef8}}, 0, 0},
+		{0x00, (0x1d << 3) | 0x7, {{0x60, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0},
+		{0x00, (0x1f << 3) | 0x1, {{0x60, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0},
+		{0x00, (0x1f << 3) | 0x2, {{0x00, 0x0000}, {0x61, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0},
+	}
+};
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+	return copy_pirq_routing_table(addr);
+}
diff --git a/src/mainboard/asus/dsbf/mainboard.c b/src/mainboard/asus/dsbf/mainboard.c
new file mode 100644
index 0000000000..27a26f92c9
--- /dev/null
+++ b/src/mainboard/asus/dsbf/mainboard.c
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <arch/io.h>
+#include <boot/tables.h>
+#include <delay.h>
+#include <arch/coreboot_tables.h>
+#include "chip.h"
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <arch/io.h>
+
+static void mainboard_enable(device_t dev)
+{
+}
+
+struct chip_operations mainboard_ops = {
+	CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER)
+	.enable_dev = mainboard_enable,
+};
+
diff --git a/src/mainboard/asus/dsbf/mptable.c b/src/mainboard/asus/dsbf/mptable.c
new file mode 100644
index 0000000000..e69de29bb2
--- /dev/null
+++ b/src/mainboard/asus/dsbf/mptable.c
diff --git a/src/mainboard/asus/dsbf/romstage.c b/src/mainboard/asus/dsbf/romstage.c
new file mode 100644
index 0000000000..5251025793
--- /dev/null
+++ b/src/mainboard/asus/dsbf/romstage.c
@@ -0,0 +1,147 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <device/pci_def.h>
+#include <device/pnp_def.h>
+#include <cpu/x86/lapic.h>
+#include <lib.h>
+#include <console/console.h>
+#include <cpu/x86/bist.h>
+#include <superio/winbond/w83627hf/early_serial.c>
+#include <northbridge/intel/i5000/raminit.h>
+#include "northbridge/intel/i3100/i3100.h"
+#include "southbridge/intel/i3100/i3100.h"
+#include <southbridge/intel/i3100/early_smbus.c>
+
+#define DEVPRES_CONFIG  (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0)
+#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
+
+#define RCBA_RPC   0x0224 /* 32 bit */
+#define RCBA_HPTC  0x3404 /* 32 bit */
+#define RCBA_GCS   0x3410 /* 32 bit */
+#define RCBA_FD    0x3418 /* 32 bit */
+
+static void early_config(void)
+{
+	u32 gcs, rpc, fd;
+
+	/* Enable RCBA */
+	pci_write_config32(PCI_DEV(0, 0x1F, 0), RCBA, DEFAULT_RCBA | 1);
+
+	/* Disable watchdog */
+	gcs = read32(DEFAULT_RCBA + RCBA_GCS);
+	gcs |= (1 << 5); /* No reset */
+	write32(DEFAULT_RCBA + RCBA_GCS, gcs);
+
+	/* Configure PCIe port B as 4x */
+	rpc = read32(DEFAULT_RCBA + RCBA_RPC);
+	rpc |= (3 << 0);
+	write32(DEFAULT_RCBA + RCBA_RPC, rpc);
+
+	/* Disable Modem, Audio, PCIe ports 2/3/4 */
+	fd = read32(DEFAULT_RCBA + RCBA_FD);
+	fd |= (1 << 19) | (1 << 18) | (1 << 17) | (1 << 6) | (1 << 5);
+	write32(DEFAULT_RCBA + RCBA_FD, fd);
+
+	/* Enable HPET */
+	write32(DEFAULT_RCBA + RCBA_HPTC, (1 << 7));
+
+	/* Setup sata mode */
+	pci_write_config8(PCI_DEV(0, 0x1F, 2), SATA_MAP, 0x40);
+}
+
+#define DEFAULT_GPIOBASE 0x1180
+static void setup_gpio(void)
+{
+	pci_write_config32(PCI_DEV(0, 31, 0), 0x48, DEFAULT_GPIOBASE | 1);
+	pci_write_config8(PCI_DEV(0, 31, 0), 0x4c, (1 << 4));
+
+        outl(0x1b0ce7c0, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */
+        outl(0xec00ffff, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */
+        outl(0xff350000, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */
+        outl(0x0000e742, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */
+        outl(0x00000006, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */
+        outl(0x00000300, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */
+        outl(0x00030301, DEFAULT_GPIOBASE + 0x38); /* GPIO_LVL2 */
+
+}
+
+static void i5000_lpc_config(void)
+{
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f);
+}
+
+int mainboard_set_fbd_clock(int speed)
+{
+	switch(speed) {
+		case 533:
+			smbus_write_byte(0x6f, 0x80, 0x21);
+			return 0;
+		case 667:
+			smbus_write_byte(0x6f, 0x80, 0x23);
+			return 0;
+		default:
+			printk(BIOS_ERR, "Invalid clock: %dMHz\n", speed);
+			die("");
+			return -1;
+	}
+}
+
+void main(unsigned long bist)
+{
+	if (bist == 0)
+		enable_lapic();
+
+	i5000_lpc_config();
+
+	w83627hf_enable_serial(PNP_DEV(0x2e, 2), 0x3f8);
+
+	console_init();
+
+	/* Halt if there was a built in self test failure */
+	report_bist_failure(bist);
+
+	early_config();
+
+	setup_gpio();
+
+	enable_smbus();
+
+	/* setup PCIe MMCONF base address */
+	pci_write_config32(PCI_DEV(0, 16, 0), 0x64,
+			   CONFIG_MMCONF_BASE_ADDRESS >> 16);
+
+        smbus_write_byte(0x6f, 0x00, 0x63);
+        smbus_write_byte(0x6f, 0x01, 0x04);
+        smbus_write_byte(0x6f, 0x02, 0x53);
+        smbus_write_byte(0x6f, 0x03, 0x39);
+        smbus_write_byte(0x6f, 0x08, 0x06);
+        smbus_write_byte(0x6f, 0x09, 0x00);
+
+	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xf0, DEFAULT_RCBA | 1);
+	i5000_fbdimm_init();
+	smbus_write_byte(0x69, 0x01, 0x01);
+}