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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-02-16 08:27:50 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-04-26 06:56:35 +0000 |
| commit | 2e977807507ee33cf10826d2cd71ffc63f1fddd3 (patch) | |
| tree | 2528b85830fde1070d89b7e9ab813b68505226b1 | |
| parent | 696c642afa8558d7949a13b117066d0a732653fb (diff) | |
| download | coreboot-2e977807507ee33cf10826d2cd71ffc63f1fddd3.tar.xz | |
src/mainboard/ibase/mb899: Fix typo in comment
CR 24h Bit 0 is PNPCVS.
Change-Id: Ia79a42ed60e82a84b60f254a0895ec52c1fcda0b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/23790
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/mainboard/ibase/mb899/romstage.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index 0d3b839b8e..1b8bb954ac 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -66,7 +66,7 @@ static void early_superio_config_w83627ehg(void) dev = DUMMY_DEV; pnp_enter_conf_state(dev); - pnp_write_config(dev, 0x24, 0xc4); // PNPCSV + pnp_write_config(dev, 0x24, 0xc4); // PNPCVS pnp_write_config(dev, 0x29, 0x01); // GPIO settings pnp_write_config(dev, 0x2a, 0x40); // GPIO settings should be fc but gets set to 02 |