diff options
| author | Ronak Kanabar <ronak.kanabar@intel.com> | 2020-03-09 14:07:28 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-04-15 14:05:55 +0000 |
| commit | 31fef3f6f8a417c80bdcbebfe99d05adbb197389 (patch) | |
| tree | b8d47e5b14aa6228cbdc45cf05baf9ad02a9e6e1 | |
| parent | 6d2a51eb850e7d86da0f7c3269cae606a68cbd78 (diff) | |
| download | coreboot-31fef3f6f8a417c80bdcbebfe99d05adbb197389.tar.xz | |
mb/intel/jasperlake_rvp: Update JSLRVP USB configuration
Remove extra USB port entry because it came in from copy
patch from the previous board and configure USB over-current
pins as per JSLRVP.
Change-Id: If9df8e330d31ed81207dfdfa2ab96fd4d49f3f0c
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39403
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb | 38 |
1 files changed, 13 insertions, 25 deletions
diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index e8fc451661..f5915046ca 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -30,22 +30,20 @@ chip soc/intel/jasperlake register "DdiPortBDdc" = "1" register "DdiPortCDdc" = "1" - register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port1 - register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # USB2 WWAN - register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB2 Bluetooth - register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" # Type-C Port1 - register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-C Port2 - register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # Type-C Port3 - register "usb2_ports[6]" = "USB2_PORT_MID(OC3)" # Type-C Port4 - register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port2 - register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # USB2 Type A port1 - register "usb2_ports[9]" = "USB2_PORT_MID(OC3)" # USB2 Type A port2 + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Port1 + register "usb2_ports[1]" = "USB2_PORT_MID(OC2)" # USB2 Type A port1 + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Port2 + register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" # USB2 Type A port2 + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # USB2 Bluetooth + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # USB2 WWAN + register "usb2_ports[6]" = "USB2_PORT_MID(OC2)" # USB2 Type A port3 + register "usb2_ports[7]" = "USB2_PORT_MID(OC3)" # USB2 Type A port4 - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port1 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port2 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 WLAN - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # UNUSED - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # UNUSED + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port2 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port1 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC2)" # USB3 WWAN + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" # UNUSED register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # UNUSED # Enable Pch iSCLK @@ -196,16 +194,6 @@ chip soc/intel/jasperlake device usb 2.7 on end end chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Right Lower"" - register "type" = "UPC_TYPE_A" - device usb 2.8 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Right Upper"" - register "type" = "UPC_TYPE_A" - device usb 2.9 on end - end - chip drivers/usb/acpi register "desc" = ""USB3/2 Type-A Left Lower"" register "type" = "UPC_TYPE_A" device usb 3.0 on end |