diff options
| author | Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> | 2015-06-23 19:23:25 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-07-21 20:08:41 +0200 |
| commit | 367ddc91fffafac2c5c78df62bf34305ae11778c (patch) | |
| tree | ff37be22f208ae89aeb48946b6c7064c9c1a0319 | |
| parent | 9b71b0e0001aa8fe2b5513a1d7f2d8488b0be782 (diff) | |
| download | coreboot-367ddc91fffafac2c5c78df62bf34305ae11778c.tar.xz | |
cyan/strago: Disable wwan
Disabling the wwan gpio line
since wwan is not used.
BRANCH=none
BUG=none
TEST=wwan should not connect to network on cyan/strago.
Change-Id: I9d2e5d5b185a4622218e894d3b092afe15e09289
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9a20c602b3bb768baa38b17e21cb4e5b0d9249ef
Original-Change-Id: Ib8d5fd15a172ef898ce675a85c2ea3e5f5c79144
Original-Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/285304
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10992
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
| -rw-r--r-- | src/mainboard/google/cyan/gpio.c | 2 | ||||
| -rw-r--r-- | src/mainboard/google/cyan/gpio_pre_evt.c | 2 | ||||
| -rwxr-xr-x | src/mainboard/intel/strago/gpio.c | 2 | ||||
| -rw-r--r-- | src/mainboard/intel/strago/gpio_bcrd2.c | 2 | ||||
| -rwxr-xr-x | src/mainboard/intel/strago/gpio_dvt.c | 2 |
5 files changed, 5 insertions, 5 deletions
diff --git a/src/mainboard/google/cyan/gpio.c b/src/mainboard/google/cyan/gpio.c index 8edbad6ade..3cd319d369 100644 --- a/src/mainboard/google/cyan/gpio.c +++ b/src/mainboard/google/cyan/gpio.c @@ -94,7 +94,7 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { GPIO_NC, /* GPO FST_SPI_CS1_B */ Native_M1, /* 05 FST_SPI_D1 */ Native_M1, /* 06 FST_SPI_CS0_B */ - GPIO_OUT_HIGH, /* 07 FST_SPI_CS2_B */ + GPIO_NC, /* 07 FST_SPI_CS2_B */ GPIO_NC, /* 15 UART1_RTS_B */ Native_M2, /* 16 UART1_RXD */ GPIO_NC, /* 17 UART2_RXD */ diff --git a/src/mainboard/google/cyan/gpio_pre_evt.c b/src/mainboard/google/cyan/gpio_pre_evt.c index 2ccc5d5b2b..eb285acd3f 100644 --- a/src/mainboard/google/cyan/gpio_pre_evt.c +++ b/src/mainboard/google/cyan/gpio_pre_evt.c @@ -96,7 +96,7 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { GPIO_NC, /* GPO FST_SPI_CS1_B */ Native_M1, /* 05 FST_SPI_D1 */ Native_M1, /* 06 FST_SPI_CS0_B */ - GPIO_OUT_HIGH, /* 07 FST_SPI_CS2_B */ + GPIO_NC, /* 07 FST_SPI_CS2_B */ GPIO_NC, /* 15 UART1_RTS_B */ Native_M2, /* 16 UART1_RXD */ GPIO_NC, /* 17 UART2_RXD */ diff --git a/src/mainboard/intel/strago/gpio.c b/src/mainboard/intel/strago/gpio.c index 53d903941a..3ca07e6802 100755 --- a/src/mainboard/intel/strago/gpio.c +++ b/src/mainboard/intel/strago/gpio.c @@ -96,7 +96,7 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { GPIO_NC, /* GPO FST_SPI_CS1_B */ Native_M1, /* 05 FST_SPI_D1 */ Native_M1, /* 06 FST_SPI_CS0_B */ - GPIO_OUT_HIGH, /* 07 FST_SPI_CS2_B */ + GPIO_NC, /* 07 FST_SPI_CS2_B */ GPIO_NC, /* 15 UART1_RTS_B */ Native_M2, /* 16 UART1_RXD */ GPIO_NC, /* 17 UART2_RXD */ diff --git a/src/mainboard/intel/strago/gpio_bcrd2.c b/src/mainboard/intel/strago/gpio_bcrd2.c index 3a4123de2a..b63db0bf28 100644 --- a/src/mainboard/intel/strago/gpio_bcrd2.c +++ b/src/mainboard/intel/strago/gpio_bcrd2.c @@ -96,7 +96,7 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { GPIO_NC, /* GPO FST_SPI_CS1_B */ Native_M1, /* 05 FST_SPI_D1 */ Native_M1, /* 06 FST_SPI_CS0_B */ - GPIO_OUT_HIGH, /* 07 FST_SPI_CS2_B */ + GPIO_NC, /* 07 FST_SPI_CS2_B */ GPIO_NC, /* 15 UART1_RTS_B */ Native_M2, /* 16 UART1_RXD */ GPIO_NC, /* 17 UART2_RXD */ diff --git a/src/mainboard/intel/strago/gpio_dvt.c b/src/mainboard/intel/strago/gpio_dvt.c index 3c13f45487..920c9d4e1f 100755 --- a/src/mainboard/intel/strago/gpio_dvt.c +++ b/src/mainboard/intel/strago/gpio_dvt.c @@ -94,7 +94,7 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { GPIO_NC, /* GPO FST_SPI_CS1_B */ Native_M1, /* 05 FST_SPI_D1 */ Native_M1, /* 06 FST_SPI_CS0_B */ - GPIO_OUT_HIGH, /* 07 FST_SPI_CS2_B */ + GPIO_NC, /* 07 FST_SPI_CS2_B */ GPIO_NC, /* 15 UART1_RTS_B */ Native_M2, /* 16 UART1_RXD */ GPIO_NC, /* 17 UART2_RXD */ |