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| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2017-10-27 17:12:43 -0600 |
|---|---|---|
| committer | Marshall Dawson <marshalldawson3rd@gmail.com> | 2017-11-01 21:59:08 +0000 |
| commit | 383ef6eef88fb285b3ba07a5d935e9285398b3fe (patch) | |
| tree | 66affd7cd2a07aae43f6a6614bf28639ca6265e0 | |
| parent | 7d06a3fe5a1b44e5ee475f9659a49ea1f7f58207 (diff) | |
| download | coreboot-383ef6eef88fb285b3ba07a5d935e9285398b3fe.tar.xz | |
amd/stoneyridge: Remove duplicate LPC decode setup
Delete the LPC I/O decode configuration from fixme.c. This code is
superseded by early_setup.c.
Change-Id: I86ac5e997c98fea853659bc66b13128f0872f571
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
| -rw-r--r-- | src/soc/amd/stoneyridge/fixme.c | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/src/soc/amd/stoneyridge/fixme.c b/src/soc/amd/stoneyridge/fixme.c index d3f5f6c919..60cc2d14cb 100644 --- a/src/soc/amd/stoneyridge/fixme.c +++ b/src/soc/amd/stoneyridge/fixme.c @@ -66,8 +66,6 @@ void amd_initcpuio(void) void amd_initmmio(void) { UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; AMD_CONFIG_PARAMS StdHeader; /* @@ -79,11 +77,6 @@ void amd_initmmio(void) | 1; LibAmdMsrWrite(0xc0010058, &MsrReg, &StdHeader); - /* For serial port */ - PciData = 0xff03ffd5; - PciAddress.AddressValue = MAKE_SBDFO(0, 0, PCU_DEV, LPC_FUNC, 0x44); - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - /* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; LibAmdMsrWrite(0x20c, &MsrReg, &StdHeader); |