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authorFurquan Shaikh <furquan@chromium.org>2017-08-18 17:26:27 -0700
committerFurquan Shaikh <furquan@google.com>2017-08-21 04:40:02 +0000
commit3f09b0ffef990286ecca344cf73023b35be42406 (patch)
treeb3963c08ff89e1599e33f3257594bf5aad07d1ff
parentb15769186c7767d6408e9a524eed09978db3fa60 (diff)
downloadcoreboot-3f09b0ffef990286ecca344cf73023b35be42406.tar.xz
mainboard/google/poppy: Update VR config settings
Update Psi2Threshold, IccMax, ACLoadline and DCLoadline VR config settings to match that of soraka. BUG=b:62063434 BRANCH=None TEST=Build and boot poppy. Change-Id: I2c294eb14257d319e1e2d4d1e529481d921ba6f8 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/21105 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
-rw-r--r--src/mainboard/google/poppy/variants/baseboard/devicetree.cb30
1 files changed, 20 insertions, 10 deletions
diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
index 9d5b5b0b0f..d67c9c0ae4 100644
--- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
@@ -75,65 +75,75 @@ chip soc/intel/skylake
#| Domain/Setting | SA | IA | GTUS | GTS |
#+----------------+-------+-------+-------+-------+
#| Psi1Threshold | 20A | 20A | 20A | 20A |
- #| Psi2Threshold | 4A | 5A | 5A | 5A |
+ #| Psi2Threshold | 2A | 2A | 2A | 2A |
#| Psi3Threshold | 1A | 1A | 1A | 1A |
#| Psi3Enable | 1 | 1 | 1 | 1 |
#| Psi4Enable | 1 | 1 | 1 | 1 |
#| ImonSlope | 0 | 0 | 0 | 0 |
#| ImonOffset | 0 | 0 | 0 | 0 |
- #| IccMax | 7A | 34A | 35A | 35A |
+ #| IccMax | 5A | 24A | 24A | 24A |
#| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
+ #| AcLoadline | 15 | 5.7 | 5.5 | 5.5 |
+ #| DcLoadline | 14.3 | 4.83 | 4.2 | 4.2 |
#+----------------+-------+-------+-------+-------+
register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
.vr_config_enable = 1,
.psi1threshold = VR_CFG_AMP(20),
- .psi2threshold = VR_CFG_AMP(4),
+ .psi2threshold = VR_CFG_AMP(2),
.psi3threshold = VR_CFG_AMP(1),
.psi3enable = 1,
.psi4enable = 1,
.imon_slope = 0x0,
.imon_offset = 0x0,
- .icc_max = VR_CFG_AMP(7),
+ .icc_max = VR_CFG_AMP(5),
.voltage_limit = 1520,
+ .ac_loadline = 1500,
+ .dc_loadline = 1430,
}"
register "domain_vr_config[VR_IA_CORE]" = "{
.vr_config_enable = 1,
.psi1threshold = VR_CFG_AMP(20),
- .psi2threshold = VR_CFG_AMP(5),
+ .psi2threshold = VR_CFG_AMP(2),
.psi3threshold = VR_CFG_AMP(1),
.psi3enable = 1,
.psi4enable = 1,
.imon_slope = 0x0,
.imon_offset = 0x0,
- .icc_max = VR_CFG_AMP(34),
+ .icc_max = VR_CFG_AMP(24),
.voltage_limit = 1520,
+ .ac_loadline = 570,
+ .dc_loadline = 483,
}"
register "domain_vr_config[VR_GT_UNSLICED]" = "{
.vr_config_enable = 1,
.psi1threshold = VR_CFG_AMP(20),
- .psi2threshold = VR_CFG_AMP(5),
+ .psi2threshold = VR_CFG_AMP(2),
.psi3threshold = VR_CFG_AMP(1),
.psi3enable = 1,
.psi4enable = 1,
.imon_slope = 0x0,
.imon_offset = 0x0,
- .icc_max = VR_CFG_AMP(35),
+ .icc_max = VR_CFG_AMP(24),
.voltage_limit = 1520,
+ .ac_loadline = 550,
+ .dc_loadline = 420,
}"
register "domain_vr_config[VR_GT_SLICED]" = "{
.vr_config_enable = 1,
.psi1threshold = VR_CFG_AMP(20),
- .psi2threshold = VR_CFG_AMP(5),
+ .psi2threshold = VR_CFG_AMP(2),
.psi3threshold = VR_CFG_AMP(1),
.psi3enable = 1,
.psi4enable = 1,
.imon_slope = 0x0,
.imon_offset = 0x0,
- .icc_max = VR_CFG_AMP(35),
+ .icc_max = VR_CFG_AMP(24),
.voltage_limit = 1520,
+ .ac_loadline = 550,
+ .dc_loadline = 420,
}"
# Enable Root port 1.