arch/x86: fix cmos post logging in non romcc bootblock

cmos_post_init() is called in src/arch/x86/bootblock_simple.c, and
that function is reponsible for bootstrapping the cmos post register
contents. Without this function being called none of the cmos post
functionality works correctly. Therefore, add a call to lib/bootblock.c
which the C_ENVIRONMENT_BOOTBLOCK SoCs use.

BUG=chrome-os-partner:61546

Change-Id: I2e3519f2f3f2c28e5cba26b5811f1eb0c2a90572
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/18043
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>

3 files changed, 32 insertions, 26 deletions

diff --git a/src/arch/x86/include/arch/bootblock_romcc.h b/src/arch/x86/include/arch/bootblock_romcc.h
index 54e05a1ed9..eab8a0dedf 100644
--- a/src/arch/x86/include/arch/bootblock_romcc.h
+++ b/src/arch/x86/include/arch/bootblock_romcc.h
@@ -62,29 +62,3 @@ static void sanitize_cmos(void)
 	}
 }
 #endif
-
-#if CONFIG_CMOS_POST
-static void cmos_post_init(void)
-{
-	u8 magic = CMOS_POST_BANK_0_MAGIC;
-
-	/* Switch to the other bank */
-	switch (cmos_read(CMOS_POST_BANK_OFFSET)) {
-	case CMOS_POST_BANK_1_MAGIC:
-		break;
-	case CMOS_POST_BANK_0_MAGIC:
-		magic = CMOS_POST_BANK_1_MAGIC;
-		break;
-	default:
-		/* Initialize to zero */
-		cmos_write(0, CMOS_POST_BANK_0_OFFSET);
-		cmos_write(0, CMOS_POST_BANK_1_OFFSET);
-#if CONFIG_CMOS_POST_EXTRA
-		cmos_write32(CMOS_POST_BANK_0_EXTRA, 0);
-		cmos_write32(CMOS_POST_BANK_1_EXTRA, 0);
-#endif
-	}
-
-	cmos_write(magic, CMOS_POST_BANK_OFFSET);
-}
-#endif
diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h
index 66d5edb4b9..99fba9dbe5 100644
--- a/src/include/pc80/mc146818rtc.h
+++ b/src/include/pc80/mc146818rtc.h
@@ -221,10 +221,39 @@ unsigned read_option_lowlevel(unsigned start, unsigned size, unsigned def);
 #define CMOS_POST_EXTRA_DEV_PATH  0x01
 
 void cmos_post_log(void);
+
+/* cmos_post_init() is exposed in this manner because it also needs to be called
+ * by bootblock code compiled by romcc. */
+static inline void cmos_post_init(void)
+{
+	u8 magic = CMOS_POST_BANK_0_MAGIC;
+
+	/* Switch to the other bank */
+	switch (cmos_read(CMOS_POST_BANK_OFFSET)) {
+	case CMOS_POST_BANK_1_MAGIC:
+		break;
+	case CMOS_POST_BANK_0_MAGIC:
+		magic = CMOS_POST_BANK_1_MAGIC;
+		break;
+	default:
+		/* Initialize to zero */
+		cmos_write(0, CMOS_POST_BANK_0_OFFSET);
+		cmos_write(0, CMOS_POST_BANK_1_OFFSET);
+#if CONFIG_CMOS_POST_EXTRA
+		cmos_write32(CMOS_POST_BANK_0_EXTRA, 0);
+		cmos_write32(CMOS_POST_BANK_1_EXTRA, 0);
+#endif
+	}
+
+	cmos_write(magic, CMOS_POST_BANK_OFFSET);
+}
 #else
 static inline void cmos_post_log(void) {}
+static inline void cmos_post_init(void) {}
 #endif /* CONFIG_CMOS_POST */
 
+#else /* !CONFIG_ARCH_X86 */
+static inline void cmos_post_init(void) {}
 #endif /* CONFIG_ARCH_X86 */
 
 #endif /*  PC80_MC146818RTC_H */
diff --git a/src/lib/bootblock.c b/src/lib/bootblock.c
index 9dece0c373..a560152332 100644
--- a/src/lib/bootblock.c
+++ b/src/lib/bootblock.c
@@ -18,6 +18,7 @@
 #include <bootblock_common.h>
 #include <console/console.h>
 #include <delay.h>
+#include <pc80/mc146818rtc.h>
 #include <program_loading.h>
 #include <symbols.h>
 #include <timestamp.h>
@@ -35,6 +36,8 @@ void asmlinkage bootblock_main_with_timestamp(uint64_t base_timestamp)
 	if (IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS) && _timestamp_size > 0)
 		timestamp_init(base_timestamp);
 
+	cmos_post_init();
+
 	bootblock_soc_early_init();
 	bootblock_mainboard_early_init();