diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2018-01-17 15:27:18 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2018-01-18 20:43:25 +0000 |
| commit | 4c65398c10fa4583ad6b83ddc7f7873625a6ddbf (patch) | |
| tree | 231111b2f558d99ddb06f9bb7cb45564c9b72e98 | |
| parent | a9d4e2adce13ac467647caa0449726844016aa39 (diff) | |
| download | coreboot-4c65398c10fa4583ad6b83ddc7f7873625a6ddbf.tar.xz | |
Intel i82810 boards & chips: Remove - using LATE_CBMEM_INIT
All boards and chips that are still using LATE_CBMEM_INIT are being
removed as previously discussed.
If these boards and chips are updated to not use LATE_CBMEM_INIT, they
can be restored to the active codebase from the 4.7 branch.
chips:
northbridge/intel/i82810
Mainboards:
src/mainboard/asus/mew-am
src/mainboard/asus/mew-vm
src/mainboard/ecs/p6iwp-fe
src/mainboard/hp/e_vectra_p2706t
src/mainboard/intel/d810e2cb
src/mainboard/mitac/6513wu
src/mainboard/msi/ms6178
src/mainboard/nec/powermate2000
Change-Id: Ib273316c59f499e6cd3a0e4c4dc4c2cce94ff291
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/23300
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
64 files changed, 0 insertions, 2825 deletions
diff --git a/src/mainboard/asus/mew-am/Kconfig b/src/mainboard/asus/mew-am/Kconfig deleted file mode 100644 index 938dfde2b7..0000000000 --- a/src/mainboard/asus/mew-am/Kconfig +++ /dev/null @@ -1,38 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -if BOARD_ASUS_MEW_AM - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select CPU_INTEL_SOCKET_PGA370 - select NORTHBRIDGE_INTEL_I82810 - select SOUTHBRIDGE_INTEL_I82801AX - select SUPERIO_SMSC_SMSCSUPERIO - select HAVE_PIRQ_TABLE - select BOARD_ROMSIZE_KB_512 - -config MAINBOARD_DIR - string - default asus/mew-am - -config MAINBOARD_PART_NUMBER - string - default "MEW-AM" - -config IRQ_SLOT_COUNT - int - default 8 - -endif # BOARD_ASUS_MEW_AM diff --git a/src/mainboard/asus/mew-am/Kconfig.name b/src/mainboard/asus/mew-am/Kconfig.name deleted file mode 100644 index 819e73bfe0..0000000000 --- a/src/mainboard/asus/mew-am/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_ASUS_MEW_AM - bool "MEW-AM" diff --git a/src/mainboard/asus/mew-am/board_info.txt b/src/mainboard/asus/mew-am/board_info.txt deleted file mode 100644 index 1102fad96f..0000000000 --- a/src/mainboard/asus/mew-am/board_info.txt +++ /dev/null @@ -1,6 +0,0 @@ -Category: desktop -Board URL: ftp://ftp.asus.com.tw/pub/ASUS/mb/sock370/810/mew-am/ -ROM package: PLCC -ROM socketed: y -Flashrom support: n -Release year: 2004 diff --git a/src/mainboard/asus/mew-am/devicetree.cb b/src/mainboard/asus/mew-am/devicetree.cb deleted file mode 100644 index 8a20cab8a1..0000000000 --- a/src/mainboard/asus/mew-am/devicetree.cb +++ /dev/null @@ -1,60 +0,0 @@ -chip northbridge/intel/i82810 # Northbridge - device cpu_cluster 0 on # APIC cluster - chip cpu/intel/socket_PGA370 # CPU - device lapic 0 on end # APIC - end - end - device domain 0 on # PCI domain - device pci 0.0 on end # Graphics Memory Controller Hub (GMCH) - device pci 1.0 on end # Chipset Graphics Controller (CGC) - chip southbridge/intel/i82801ax # Southbridge - register "ide0_enable" = "1" - register "ide1_enable" = "1" - - device pci 1e.0 on end # PCI bridge - device pci 1f.0 on # ISA bridge - chip superio/smsc/smscsuperio # Super I/O - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.3 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 4 - end - device pnp 2e.4 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.5 on # COM2 / IR - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.7 on # PS/2 keyboard / mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt - end - device pnp 2e.9 on # Game port - io 0x60 = 0x201 - end - device pnp 2e.a on # Power-management events (PME) - io 0x60 = 0x600 - end - device pnp 2e.b on # MIDI port (MPU-401) - io 0x60 = 0x330 - irq 0x70 = 5 - end - end - end - device pci 1f.1 on end # IDE - device pci 1f.2 on end # USB - device pci 1f.3 on end # SMbus - device pci 1f.5 off end # AC'97 audio (N/A, uses CS4280 chip) - device pci 1f.6 off end # AC'97 modem (N/A) - end - end -end diff --git a/src/mainboard/asus/mew-am/irq_tables.c b/src/mainboard/asus/mew-am/irq_tables.c deleted file mode 100644 index 4af829baa8..0000000000 --- a/src/mainboard/asus/mew-am/irq_tables.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/pirq_routing.h> - -static const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, - PIRQ_VERSION, - 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ - 0x00, /* Interrupt router bus */ - (0x1f << 3) | 0x0, /* Interrupt router device */ - 0, /* IRQs devoted exclusively to PCI usage */ - 0x8086, /* Vendor */ - 0x122e, /* Device */ - 0, /* Miniport data */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0xe3, /* Checksum */ - { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x1e << 3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0}, - {0x01,(0x08 << 3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x1, 0x0}, - {0x01,(0x09 << 3)|0x0, {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x01eb8}}, 0x2, 0x0}, - {0x01,(0x0a << 3)|0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x3, 0x0}, - {0x01,(0x0b << 3)|0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x4, 0x0}, - {0x00,(0x1f << 3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0}, - {0x00,(0x01 << 3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0}, - {0x01,(0x02 << 3)|0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x0, 0x0}, - } -}; - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - return copy_pirq_routing_table(addr, &intel_irq_routing_table); -} diff --git a/src/mainboard/asus/mew-am/romstage.c b/src/mainboard/asus/mew-am/romstage.c deleted file mode 100644 index c39657b4e0..0000000000 --- a/src/mainboard/asus/mew-am/romstage.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <stdlib.h> -#include <device/pci_def.h> -#include <arch/io.h> -#include <device/pnp_def.h> -#include <console/console.h> -#include <southbridge/intel/i82801ax/i82801ax.h> -#include <northbridge/intel/i82810/raminit.h> -#include <cpu/x86/bist.h> -#include <cpu/intel/romstage.h> -#include <superio/smsc/smscsuperio/smscsuperio.h> -#include <lib.h> - -#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) - -void mainboard_romstage_entry(unsigned long bist) -{ - smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - report_bist_failure(bist); - enable_smbus(); - dump_spd_registers(); - sdram_set_registers(); - sdram_set_spd_registers(); - sdram_enable(); -} diff --git a/src/mainboard/asus/mew-vm/Kconfig b/src/mainboard/asus/mew-vm/Kconfig deleted file mode 100644 index 91a9c8b231..0000000000 --- a/src/mainboard/asus/mew-vm/Kconfig +++ /dev/null @@ -1,39 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -if BOARD_ASUS_MEW_VM - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select CPU_INTEL_SOCKET_PGA370 - select NORTHBRIDGE_INTEL_I82810 - select SOUTHBRIDGE_INTEL_I82801AX - select SUPERIO_SMSC_LPC47B272 - select HAVE_OPTION_TABLE - select HAVE_PIRQ_TABLE - select BOARD_ROMSIZE_KB_512 - -config MAINBOARD_DIR - string - default asus/mew-vm - -config MAINBOARD_PART_NUMBER - string - default "MEW-VM" - -config IRQ_SLOT_COUNT - int - default 11 - -endif # BOARD_ASUS_MEW_VM diff --git a/src/mainboard/asus/mew-vm/Kconfig.name b/src/mainboard/asus/mew-vm/Kconfig.name deleted file mode 100644 index 4966679acb..0000000000 --- a/src/mainboard/asus/mew-vm/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_ASUS_MEW_VM - bool "MEW-VM" diff --git a/src/mainboard/asus/mew-vm/board_info.txt b/src/mainboard/asus/mew-vm/board_info.txt deleted file mode 100644 index cbb761aa3f..0000000000 --- a/src/mainboard/asus/mew-vm/board_info.txt +++ /dev/null @@ -1,6 +0,0 @@ -Category: desktop -Board URL: http://www.elhvb.com/mboards/OEM/HP/manual/ASUS%20MEW-VM.htm -ROM package: PLCC -ROM socketed: y -Flashrom support: n -Release year: 2002 diff --git a/src/mainboard/asus/mew-vm/cmos.layout b/src/mainboard/asus/mew-vm/cmos.layout deleted file mode 100644 index b8ea9363a4..0000000000 --- a/src/mainboard/asus/mew-vm/cmos.layout +++ /dev/null @@ -1,28 +0,0 @@ -entries - -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#392 3 r 0 unused -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -456 1 e 1 ECC_memory -1008 16 h 0 check_sum - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew - -checksums - -checksum 392 1007 1008 diff --git a/src/mainboard/asus/mew-vm/devicetree.cb b/src/mainboard/asus/mew-vm/devicetree.cb deleted file mode 100644 index 397b9993d0..0000000000 --- a/src/mainboard/asus/mew-vm/devicetree.cb +++ /dev/null @@ -1,51 +0,0 @@ -chip northbridge/intel/i82810 - device domain 0 on - device pci 0.0 on end # Host bridge - device pci 1.0 on # Onboard Video - # device pci 1.0 on end - end - chip southbridge/intel/i82801ax # Southbridge - register "ide0_enable" = "1" - register "ide1_enable" = "1" - - device pci 1e.0 on # PCI Bridge - # device pci 1.0 on end - end - device pci 1f.0 on # ISA/LPC? Bridge - chip superio/smsc/lpc47b272 - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.3 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.5 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.7 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # Keyboard interrupt - irq 0x72 = 12 # Mouse interrupt - end - device pnp 2e.a off end # ACPI - end - end - device pci 1f.1 on end # IDE - device pci 1f.2 on end # USB - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # AC'97, no header on MEW-VM - device pci 1f.6 off end # AC'97 Modem (MC'97) - end - end - chip cpu/intel/socket_PGA370 - end -end diff --git a/src/mainboard/asus/mew-vm/irq_tables.c b/src/mainboard/asus/mew-vm/irq_tables.c deleted file mode 100644 index 7ebc2d53d6..0000000000 --- a/src/mainboard/asus/mew-vm/irq_tables.c +++ /dev/null @@ -1,35 +0,0 @@ -#include <arch/pirq_routing.h> - -static const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ - 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ - 0x00, /* Where the interrupt router lies (bus) */ - (0x11 << 3)|0x0, /* Where the interrupt router lies (dev) */ - 0xe20, /* IRQs devoted exclusively to PCI usage */ - 0x8086, /* Vendor */ - 0x7120, /* Device */ - 0, /* Miniport data */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x89, /* u8 checksum , this has to set to some value -that would give 0 after the sum of all bytes for this structure (including checksum) */ - { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x08 << 3)|0x0, {{0x02, 0xdea0}, {0x03, 0xdea0}, {0x04, 0xdea0}, {0x01, 0x0dea0}}, 0x1, 0x0}, - {0x00,(0x09 << 3)|0x0, {{0x03, 0xdea0}, {0x04, 0xdea0}, {0x01, 0xdea0}, {0x02, 0x0dea0}}, 0x2, 0x0}, - {0x00,(0x0a << 3)|0x0, {{0x04, 0xdea0}, {0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0x0dea0}}, 0x3, 0x0}, - {0x00,(0x0b << 3)|0x0, {{0x04, 0xdea0}, {0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0x0dea0}}, 0x4, 0x0}, - {0x00,(0x0c << 3)|0x0, {{0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0xdea0}, {0x04, 0x0dea0}}, 0x5, 0x0}, - {0x00,(0x0d << 3)|0x0, {{0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0xdea0}, {0x04, 0x0dea0}}, 0x6, 0x0}, - {0x00,(0x11 << 3)|0x0, {{0x00, 0xdea0}, {0x00, 0xdea0}, {0x03, 0xdea0}, {0x04, 0x0dea0}}, 0x0, 0x0}, - {0x00,(0x0f << 3)|0x0, {{0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0xdea0}, {0x04, 0x0dea0}}, 0x0, 0x0}, - {0x00,(0x01 << 3)|0x0, {{0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0xdea0}, {0x04, 0x0dea0}}, 0x0, 0x0}, - {0x00,(0x10 << 3)|0x0, {{0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0xdea0}, {0x04, 0x0dea0}}, 0x0, 0x0}, - {0x00,(0x12 << 3)|0x0, {{0x01, 0xdea0}, {0x00, 0xdea0}, {0x00, 0xdea0}, {0x00, 0x0dea0}}, 0x0, 0x0}, - } -}; - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - return copy_pirq_routing_table(addr, &intel_irq_routing_table); -} diff --git a/src/mainboard/asus/mew-vm/romstage.c b/src/mainboard/asus/mew-vm/romstage.c deleted file mode 100644 index 947003992a..0000000000 --- a/src/mainboard/asus/mew-vm/romstage.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <device/pci_def.h> -#include <arch/io.h> -#include <device/pnp_def.h> -#include <stdlib.h> -#include <console/console.h> -#include <superio/smsc/lpc47b272/lpc47b272.h> -#include <northbridge/intel/i82810/raminit.h> -#include <cpu/x86/bist.h> -#include <cpu/intel/romstage.h> -#include <southbridge/intel/i82801ax/i82801ax.h> -#include <lib.h> - -#define SERIAL_DEV PNP_DEV(0x2e, LPC47B272_SP1) - -void mainboard_romstage_entry(unsigned long bist) -{ - lpc47b272_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - enable_smbus(); - report_bist_failure(bist); - dump_spd_registers(); - sdram_set_registers(); - sdram_set_spd_registers(); - sdram_enable(); -} diff --git a/src/mainboard/ecs/Kconfig b/src/mainboard/ecs/Kconfig deleted file mode 100644 index c570ce2bce..0000000000 --- a/src/mainboard/ecs/Kconfig +++ /dev/null @@ -1,31 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -if VENDOR_ECS - -choice - prompt "Mainboard model" - -source "src/mainboard/ecs/*/Kconfig.name" - -endchoice - -source "src/mainboard/ecs/*/Kconfig" - -config MAINBOARD_VENDOR - string - default "ECS" - -endif # VENDOR_ECS diff --git a/src/mainboard/ecs/Kconfig.name b/src/mainboard/ecs/Kconfig.name deleted file mode 100644 index 778c3691b2..0000000000 --- a/src/mainboard/ecs/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config VENDOR_ECS - bool "ECS" diff --git a/src/mainboard/ecs/p6iwp-fe/Kconfig b/src/mainboard/ecs/p6iwp-fe/Kconfig deleted file mode 100644 index 9afae9a039..0000000000 --- a/src/mainboard/ecs/p6iwp-fe/Kconfig +++ /dev/null @@ -1,39 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2010 Anders Jenbo <anders@jenbo.dk> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -if BOARD_ECS_P6IWP_FE - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select CPU_INTEL_SOCKET_PGA370 - select NORTHBRIDGE_INTEL_I82810 - select SOUTHBRIDGE_INTEL_I82801AX - select SUPERIO_ITE_IT8712F - select HAVE_PIRQ_TABLE - select BOARD_ROMSIZE_KB_512 - -config MAINBOARD_DIR - string - default ecs/p6iwp-fe - -config MAINBOARD_PART_NUMBER - string - default "P6IWP-FE" - -config IRQ_SLOT_COUNT - int - default 10 - -endif # BOARD_ECS_P6IWP_FE diff --git a/src/mainboard/ecs/p6iwp-fe/Kconfig.name b/src/mainboard/ecs/p6iwp-fe/Kconfig.name deleted file mode 100644 index 66fc8c3241..0000000000 --- a/src/mainboard/ecs/p6iwp-fe/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_ECS_P6IWP_FE - bool "P6IWP-Fe" diff --git a/src/mainboard/ecs/p6iwp-fe/board_info.txt b/src/mainboard/ecs/p6iwp-fe/board_info.txt deleted file mode 100644 index 31ce6e4154..0000000000 --- a/src/mainboard/ecs/p6iwp-fe/board_info.txt +++ /dev/null @@ -1,6 +0,0 @@ -Category: desktop -Board URL: http://www.ecs.com.tw/ECSWebSite/Product/Product_Detail.aspx?CategoryID=1&DetailID=95&DetailName=Feature&MenuID=24&LanID=4 -ROM package: PLCC -ROM protocol: FWH -ROM socketed: y -Flashrom support: y diff --git a/src/mainboard/ecs/p6iwp-fe/devicetree.cb b/src/mainboard/ecs/p6iwp-fe/devicetree.cb deleted file mode 100644 index 9c36a20285..0000000000 --- a/src/mainboard/ecs/p6iwp-fe/devicetree.cb +++ /dev/null @@ -1,82 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2010 Anders Jenbo <anders@jenbo.dk> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -chip northbridge/intel/i82810 # Northbridge - device cpu_cluster 0 on # APIC cluster - chip cpu/intel/socket_PGA370 # CPU - device lapic 0 on end # APIC - end - end - device domain 0 on # PCI domain - device pci 0.0 on end # Graphics Memory Controller Hub (GMCH) - device pci 1.0 on end # Chipset Graphics Controller (CGC) - chip southbridge/intel/i82801ax # Southbridge - register "ide0_enable" = "1" - register "ide1_enable" = "1" - - device pci 1e.0 on end # PCI bridge - device pci 1f.0 on # ISA bridge - chip superio/ite/it8712f # Super I/O - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 on # EC - io 0x60 = 0x290 - io 0x62 = 0x230 - irq 0x70 = 9 - end - device pnp 2e.5 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.6 on # PS/2 mouse - irq 0x70 = 12 - end - device pnp 2e.7 on # GPIO - io 0x62 = 0x1220 - io 0x64 = 0x1200 - end - device pnp 2e.8 off # MIDI - io 0x60 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.9 off # Game port - io 0x60 = 0x220 - end - device pnp 2e.a off end # CIR - end - end - device pci 1f.1 on end # IDE - device pci 1f.2 on end # USB - device pci 1f.3 on end # SMBus - end - end -end diff --git a/src/mainboard/ecs/p6iwp-fe/irq_tables.c b/src/mainboard/ecs/p6iwp-fe/irq_tables.c deleted file mode 100644 index 23ffbb156e..0000000000 --- a/src/mainboard/ecs/p6iwp-fe/irq_tables.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Anders Jenbo <anders@jenbo.dk> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/pirq_routing.h> - -static const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ - 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus */ - 0x00, /* Interrupt router bus */ - (0x1f << 3) | 0x0, /* Interrupt router dev */ - 0x1c00, /* IRQs devoted exclusively to PCI usage */ - 0x8086, /* Vendor */ - 0x7000, /* Device */ - 0, /* Miniport */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x7, /* Checksum (has to be set to some value that - * would give 0 after the sum of all bytes - * for this structure (including checksum). - */ - { - /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00, (0x1e << 3) | 0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}}, 0x1, 0x0}, - {0x00, (0x10 << 3) | 0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}}, 0x2, 0x0}, - {0x01, (0x04 << 3) | 0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}}, 0x3, 0x0}, - {0x01, (0x05 << 3) | 0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}}, 0x4, 0x0}, - {0x01, (0x0a << 3) | 0x0, {{0x63, 0xdeb8}, {0x62, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}}, 0x5, 0x0}, - {0x01, (0x07 << 3) | 0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}}, 0x6, 0x0}, - {0x01, (0x08 << 3) | 0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}}, 0x7, 0x0}, - {0x01, (0x09 << 3) | 0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}}, 0x8, 0x0}, - {0x00, (0x01 << 3) | 0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}}, 0x0, 0x0}, - {0x00, (0x1f << 3) | 0x1, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}}, 0x0, 0x0}, - } -}; - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - return copy_pirq_routing_table(addr, &intel_irq_routing_table); -} diff --git a/src/mainboard/ecs/p6iwp-fe/romstage.c b/src/mainboard/ecs/p6iwp-fe/romstage.c deleted file mode 100644 index f092e1483e..0000000000 --- a/src/mainboard/ecs/p6iwp-fe/romstage.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de> - * Copyright (C) 2010 Anders Jenbo <anders@jenbo.dk> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <stdlib.h> -#include <device/pci_def.h> -#include <arch/io.h> -#include <device/pnp_def.h> -#include <console/console.h> -#include <southbridge/intel/i82801ax/i82801ax.h> -#include <northbridge/intel/i82810/raminit.h> -#include <cpu/x86/bist.h> -#include <cpu/intel/romstage.h> -#include <superio/ite/common/ite.h> -#include <superio/ite/it8712f/it8712f.h> -#include <lib.h> - -#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) -#define CLKIN_DEV PNP_DEV(0x2e, IT8712F_GPIO) - -void mainboard_romstage_entry(unsigned long bist) -{ - ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24); - ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - report_bist_failure(bist); - enable_smbus(); - dump_spd_registers(); - sdram_set_registers(); - sdram_set_spd_registers(); - sdram_enable(); - dump_spd_registers(); -} diff --git a/src/mainboard/hp/e_vectra_p2706t/Kconfig b/src/mainboard/hp/e_vectra_p2706t/Kconfig deleted file mode 100644 index 28594f019d..0000000000 --- a/src/mainboard/hp/e_vectra_p2706t/Kconfig +++ /dev/null @@ -1,42 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -# FIXME: It's a PC87360 actually. -# FIXME: It's an i810E actually! -# FIXME: ROM chip size really 512KB? -if BOARD_HP_E_VECTRA_P2706T - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select CPU_INTEL_SOCKET_PGA370 - select NORTHBRIDGE_INTEL_I82810 - select SOUTHBRIDGE_INTEL_I82801AX - select SUPERIO_NSC_PC87360 - select HAVE_PIRQ_TABLE - select BOARD_ROMSIZE_KB_512 - -config MAINBOARD_DIR - string - default hp/e_vectra_p2706t - -config MAINBOARD_PART_NUMBER - string - default "e-Vectra P2706T" - -config IRQ_SLOT_COUNT - int - default 3 - -endif # BOARD_HP_E_VECTRA_P2706T diff --git a/src/mainboard/hp/e_vectra_p2706t/Kconfig.name b/src/mainboard/hp/e_vectra_p2706t/Kconfig.name deleted file mode 100644 index f37ab1ef0c..0000000000 --- a/src/mainboard/hp/e_vectra_p2706t/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_HP_E_VECTRA_P2706T - bool "e-Vectra P2706T" diff --git a/src/mainboard/hp/e_vectra_p2706t/board_info.txt b/src/mainboard/hp/e_vectra_p2706t/board_info.txt deleted file mode 100644 index 4df7a1ec9d..0000000000 --- a/src/mainboard/hp/e_vectra_p2706t/board_info.txt +++ /dev/null @@ -1,2 +0,0 @@ -Category: desktop -Release year: 2000 diff --git a/src/mainboard/hp/e_vectra_p2706t/devicetree.cb b/src/mainboard/hp/e_vectra_p2706t/devicetree.cb deleted file mode 100644 index 04d6d8d689..0000000000 --- a/src/mainboard/hp/e_vectra_p2706t/devicetree.cb +++ /dev/null @@ -1,58 +0,0 @@ -# TODO: i810E actually! -chip northbridge/intel/i82810 # Northbridge - device cpu_cluster 0 on # APIC cluster - chip cpu/intel/socket_PGA370 # CPU - device lapic 0 on end # APIC - end - end - device domain 0 on - device pci 0.0 on end # Host bridge - device pci 1.0 on end # Onboard VGA - chip southbridge/intel/i82801ax # Southbridge - register "ide0_enable" = "1" - register "ide1_enable" = "1" - - device pci 1e.0 on end # PCI bridge - device pci 1f.0 on # ISA/LPC bridge - # TODO: PC87364 actually! - # TODO: Check Super I/O settings and compare to superiotool -d. - chip superio/nsc/pc87360 # Super I/O - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 2e.2 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.4 off end # SWC - device pnp 2e.5 off end # PS/2 mouse - device pnp 2e.6 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.7 off end # GPIO - device pnp 2e.8 off end # ACB - device pnp 2e.9 off end # FSCM - device pnp 2e.a off end # WDT - end - end - device pci 1f.1 on end # IDE - device pci 1f.2 on end # USB - device pci 1f.3 on end # SMBus - device pci 1f.5 on end # AC'97 audio - device pci 1f.6 off end # AC'97 modem (N/A ?) - end - end -end diff --git a/src/mainboard/hp/e_vectra_p2706t/irq_tables.c b/src/mainboard/hp/e_vectra_p2706t/irq_tables.c deleted file mode 100644 index 18e2c504fc..0000000000 --- a/src/mainboard/hp/e_vectra_p2706t/irq_tables.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/pirq_routing.h> - -static const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, - PIRQ_VERSION, - 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ - 0x00, /* Interrupt router bus */ - (0x1f << 3) | 0x0, /* Interrupt router device */ - 0x0, /* IRQs devoted exclusively to PCI usage */ - 0x8086, /* Vendor */ - 0x2410, /* Device */ - 0, /* Miniport data */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x59, /* Checksum */ - { - /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00, (0x01 << 3) | 0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}}, 0x0, 0x0}, - {0x00, (0x1e << 3) | 0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}}, 0x0, 0x0}, - {0x00, (0x1f << 3) | 0x0, {{0xfe, 0x4000}, {0x61, 0xdeb8}, {0x00, 0x0000}, {0x63, 0xdeb8}}, 0x0, 0x0}, - } -}; - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - return copy_pirq_routing_table(addr, &intel_irq_routing_table); -} diff --git a/src/mainboard/hp/e_vectra_p2706t/romstage.c b/src/mainboard/hp/e_vectra_p2706t/romstage.c deleted file mode 100644 index 1d3c3fd5c2..0000000000 --- a/src/mainboard/hp/e_vectra_p2706t/romstage.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <device/pci_def.h> -#include <arch/io.h> -#include <device/pnp_def.h> -#include <stdlib.h> -#include <console/console.h> -/* TODO: It's a PC87364 actually! */ -#include <superio/nsc/pc87360/pc87360.h> -/* TODO: It's i810E actually! */ -#include <northbridge/intel/i82810/raminit.h> -#include <cpu/x86/bist.h> -#include <cpu/intel/romstage.h> -#include <southbridge/intel/i82801ax/i82801ax.h> -#include <lib.h> - -/* TODO: It's a PC87364 actually! */ -#define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1) - -void mainboard_romstage_entry(unsigned long bist) -{ - /* TODO: It's a PC87364 actually! */ - pc87360_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - enable_smbus(); - report_bist_failure(bist); - dump_spd_registers(); - sdram_set_registers(); - sdram_set_spd_registers(); - sdram_enable(); -} diff --git a/src/mainboard/intel/d810e2cb/Kconfig b/src/mainboard/intel/d810e2cb/Kconfig deleted file mode 100644 index 8695da962c..0000000000 --- a/src/mainboard/intel/d810e2cb/Kconfig +++ /dev/null @@ -1,39 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2010 Joseph Smith <joe@settoplinux.org> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -if BOARD_INTEL_D810E2CB - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select CPU_INTEL_SOCKET_FC_PGA370 - select NORTHBRIDGE_INTEL_I82810 - select SOUTHBRIDGE_INTEL_I82801BX - select SUPERIO_SMSC_SMSCSUPERIO - select HAVE_PIRQ_TABLE - select USE_WATCHDOG_ON_BOOT - select BOARD_ROMSIZE_KB_512 - -config MAINBOARD_DIR - string - default intel/d810e2cb - -config MAINBOARD_PART_NUMBER - string - default "D810E2CB" - -config IRQ_SLOT_COUNT - int - default 7 - -endif # BOARD_INTEL_D810E2CB diff --git a/src/mainboard/intel/d810e2cb/Kconfig.name b/src/mainboard/intel/d810e2cb/Kconfig.name deleted file mode 100644 index 8bf8624ab8..0000000000 --- a/src/mainboard/intel/d810e2cb/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_INTEL_D810E2CB - bool "D810E2CB" diff --git a/src/mainboard/intel/d810e2cb/board_info.txt b/src/mainboard/intel/d810e2cb/board_info.txt deleted file mode 100644 index cc1327cd82..0000000000 --- a/src/mainboard/intel/d810e2cb/board_info.txt +++ /dev/null @@ -1,6 +0,0 @@ -Category: desktop -Board URL: http://downloadcenter.intel.com/Detail_Desc.aspx?agr=Y&DwnldID=17789&lang=eng&wapkw=d810e2cb -ROM package: PLCC -ROM protocol: FWH -ROM socketed: n -Release year: 1999 diff --git a/src/mainboard/intel/d810e2cb/devicetree.cb b/src/mainboard/intel/d810e2cb/devicetree.cb deleted file mode 100644 index 461a357a40..0000000000 --- a/src/mainboard/intel/d810e2cb/devicetree.cb +++ /dev/null @@ -1,78 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2010 Joseph Smith <joe@settoplinux.org> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -chip northbridge/intel/i82810 # Northbridge - device cpu_cluster 0 on # APIC cluster - chip cpu/intel/socket_FC_PGA370 # CPU - device lapic 0 on end # APIC - end - end - device domain 0 on # PCI domain - device pci 0.0 on end # Graphics Memory Controller Hub (GMCH) - device pci 1.0 on end # Chipset Graphics Controller (CGC) - chip southbridge/intel/i82801bx # Southbridge - register "pirqa_routing" = "0x05" - register "pirqb_routing" = "0x06" - register "pirqc_routing" = "0x07" - register "pirqd_routing" = "0x09" - register "pirqe_routing" = "0x0a" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x0b" - - register "ide0_enable" = "1" - register "ide1_enable" = "1" - - device pci 1e.0 on end # PCI bridge - device pci 1f.0 on # ISA bridge - chip superio/smsc/smscsuperio # Super I/O (SMSC LPC47M102) - device pnp 4e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 4e.3 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 4 - end - device pnp 4e.4 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 4e.5 off end # COM2 - device pnp 4e.7 on # PS/2 keyboard / mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt - end - device pnp 4e.9 off end # Game port - device pnp 4e.a on # Runtime registers - io 0x60 = 0x800 - end - device pnp 4e.b off end # MPU-401 - end - end - device pci 1f.1 on end # IDE - device pci 1f.2 on end # USB - device pci 1f.3 on end # SMbus - device pci 1f.4 on end # USB - device pci 1f.5 on end # Audio controller - device pci 1f.6 off end # Modem controller - end - end -end diff --git a/src/mainboard/intel/d810e2cb/gpio.c b/src/mainboard/intel/d810e2cb/gpio.c deleted file mode 100644 index 84e49d69a6..0000000000 --- a/src/mainboard/intel/d810e2cb/gpio.c +++ /dev/null @@ -1,209 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Joseph Smith <joe@settoplinux.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <delay.h> - -#define PME_DEV PNP_DEV(0x4e, 0x0a) -#define PME_IO_BASE_ADDR 0x800 /* Runtime register base address */ - -/* Early mainboard specific GPIO setup. */ -static void mb_gpio_init(void) -{ - device_t dev; - uint16_t port; - - /* Southbridge GPIOs. */ - /* Set the LPC device statically. */ - dev = PCI_DEV(0x0, 0x1f, 0x0); - - /* Set the value for GPIO base address register and enable GPIO. */ - pci_write_config32(dev, GPIO_BASE, (GPIO_BASE_ADDR | 1)); - pci_write_config8(dev, GPIO_CNTL, 0x10); - - udelay(10); - outl(0x1a203180, GPIO_BASE_ADDR + 0x00); /* GPIO_USE_SEL */ - outl(0x0000ffff, GPIO_BASE_ADDR + 0x04); /* GP_IO_SEL */ - outl(0x13bf0000, GPIO_BASE_ADDR + 0x0c); /* GP_LVL */ - outl(0x00040000, GPIO_BASE_ADDR + 0x18); /* GPO_BLINK */ - outl(0x000039ff, GPIO_BASE_ADDR + 0x2c); /* GPI_INV */ - - /* Super I/O GPIOs. */ - dev = PME_DEV; - port = dev >> 8; - - /* Enter the configuration state. */ - outb(0x55, port); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, PME_IO_BASE_ADDR); - pnp_set_enable(dev, 1); - - /* GP10 - J1B1 */ - outl(0x01, PME_IO_BASE_ADDR + 0x23); - - /* GP11 - J1B2 */ - outl(0x01, PME_IO_BASE_ADDR + 0x24); - - /* GP12 - J2B1 */ - outl(0x01, PME_IO_BASE_ADDR + 0x25); - - /* GP13 - J2B2 */ - outl(0x01, PME_IO_BASE_ADDR + 0x26); - - /* GP14 - J1X */ - outl(0x01, PME_IO_BASE_ADDR + 0x27); - - /* GP15 - J1Y */ - outl(0x01, PME_IO_BASE_ADDR + 0x28); - - /* GP16 - J2X */ - outl(0x01, PME_IO_BASE_ADDR + 0x29); - - /* GP17 - J2Y */ - outl(0x01, PME_IO_BASE_ADDR + 0x2a); - - /* GP20 - 8042 P17 */ - outl(0x01, PME_IO_BASE_ADDR + 0x2b); - - /* GP21 - 8042 P16 */ - outl(0x00, PME_IO_BASE_ADDR + 0x2c); - - /* GP22 - 8042 P12 */ - outl(0x00, PME_IO_BASE_ADDR + 0x2d); - - /* GP24 */ - outl(0x00, PME_IO_BASE_ADDR + 0x2f); - - /* GP25 - MIDI_IN */ - outl(0x01, PME_IO_BASE_ADDR + 0x30); - - /* GP26 - MIDI_OUT */ - outl(0x01, PME_IO_BASE_ADDR + 0x31); - - /* GP27 - nIO_SMI */ - outl(0x04, PME_IO_BASE_ADDR + 0x32); - - /* GP30 - FAN_TACH2 */ - outl(0x05, PME_IO_BASE_ADDR + 0x33); - - /* GP31 - FAN_TACH1 */ - outl(0x05, PME_IO_BASE_ADDR + 0x34); - - /* GP32 - FAN2 */ - outl(0x04, PME_IO_BASE_ADDR + 0x35); - - /* GP33 - FAN1 */ - outl(0x04, PME_IO_BASE_ADDR + 0x36); - - /* GP34 - IRRX2 */ - outl(0x05, PME_IO_BASE_ADDR + 0x37); - - /* GP35 - IRTX2 */ - outl(0x04, PME_IO_BASE_ADDR + 0x38); - - /* GP36 - nKBDRST */ - outl(0x84, PME_IO_BASE_ADDR + 0x39); - - /* GP37 - A20M */ - outl(0x84, PME_IO_BASE_ADDR + 0x3a); - - /* GP40 - DRVDEN0 */ - outl(0x04, PME_IO_BASE_ADDR + 0x3b); - - /* GP41 - DRVDEN1 */ - outl(0x04, PME_IO_BASE_ADDR + 0x3c); - - /* GP42 - nIO_PME */ - outl(0x84, PME_IO_BASE_ADDR + 0x3d); - - /* GP43 */ - outl(0x00, PME_IO_BASE_ADDR + 0x3e); - - /* GP50 - nIR2 */ - outl(0x05, PME_IO_BASE_ADDR + 0x3f); - - /* GP51 - nDCD2 */ - outl(0x05, PME_IO_BASE_ADDR + 0x40); - - /* GP52 - RXD2 */ - outl(0x05, PME_IO_BASE_ADDR + 0x41); - - /* GP53 - TXD2 */ - outl(0x04, PME_IO_BASE_ADDR + 0x42); - - /* GP54 - nDSR2 */ - outl(0x05, PME_IO_BASE_ADDR + 0x43); - - /* GP55 - nRTS2 */ - outl(0x04, PME_IO_BASE_ADDR + 0x44); - - /* GP56 - nCTS2 */ - outl(0x05, PME_IO_BASE_ADDR + 0x45); - - /* GP57 - nDTR2 */ - outl(0x04, PME_IO_BASE_ADDR + 0x46); - - /* GP60 - LED1 */ - outl(0x84, PME_IO_BASE_ADDR + 0x47); - - /* GP61 - LED2 */ - outl(0x84, PME_IO_BASE_ADDR + 0x48); - - /* GP1 */ - outl(0x00, PME_IO_BASE_ADDR + 0x4b); - - /* GP2 */ - outl(0x14, PME_IO_BASE_ADDR + 0x4c); - - /* GP3 */ - outl(0xda, PME_IO_BASE_ADDR + 0x4d); - - /* GP4 */ - outl(0x08, PME_IO_BASE_ADDR + 0x4e); - - /* GP5 */ - outl(0x00, PME_IO_BASE_ADDR + 0x4f); - - /* GP6 */ - outl(0x00, PME_IO_BASE_ADDR + 0x50); - - /* FAN1 */ - outl(0x01, PME_IO_BASE_ADDR + 0x56); - - /* FAN2 */ - outl(0x01, PME_IO_BASE_ADDR + 0x57); - - /* Fan Control */ - outl(0xf0, PME_IO_BASE_ADDR + 0x58); - - /* Fan1 Preload */ - outl(0x00, PME_IO_BASE_ADDR + 0x5b); - - /* Fan2 Preload */ - outl(0x00, PME_IO_BASE_ADDR + 0x5c); - - /* LED1 */ - outl(0x03, PME_IO_BASE_ADDR + 0x5d); - - /* LED2 */ - outl(0x03, PME_IO_BASE_ADDR + 0x5e); - - /* Keyboard Scan Code */ - outl(0x00, PME_IO_BASE_ADDR + 0x5f); - - /* Exit the configuration state. */ - outb(0xaa, port); -} diff --git a/src/mainboard/intel/d810e2cb/irq_tables.c b/src/mainboard/intel/d810e2cb/irq_tables.c deleted file mode 100644 index 7d4de66c1e..0000000000 --- a/src/mainboard/intel/d810e2cb/irq_tables.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Joseph Smith <joe@settoplinux.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/pirq_routing.h> - -static const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ - 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus (7)*/ - 0x00, /* Interrupt router bus */ - (0x1f << 3) | 0x0, /* Interrupt router dev */ - 0, /* IRQs devoted exclusively to PCI usage */ - 0x8086, /* Vendor */ - 0x2440, /* Device */ - 0, /* Miniport */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0xd9, /* Checksum (has to be set to some value that - * would give 0 after the sum of all bytes - * for this structure (including checksum). - */ - { - /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00, (0x00 << 3) | 0x0, {{0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, - {0x00, (0x01 << 3) | 0x0, {{0x60, 0xdeb8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, - {0x00, (0x1e << 3) | 0x0, {{0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, - {0x00, (0x1f << 3) | 0x0, {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x6b, 0xdef8}, {0x63, 0xdef8}}, 0x0, 0x0}, - {0x01, (0x01 << 3) | 0x0, {{0x62, 0xdef8}, {0x63, 0xdef8}, {0x60, 0xdef8}, {0x61, 0xdef8}}, 0x1, 0x0}, - {0x01, (0x02 << 3) | 0x0, {{0x63, 0xdef8}, {0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}}, 0x2, 0x0}, - {0x01, (0x08 << 3) | 0x0, {{0x68, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, - } -}; - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - return copy_pirq_routing_table(addr, &intel_irq_routing_table); -} diff --git a/src/mainboard/intel/d810e2cb/romstage.c b/src/mainboard/intel/d810e2cb/romstage.c deleted file mode 100644 index 5bcee0c544..0000000000 --- a/src/mainboard/intel/d810e2cb/romstage.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Joseph Smith <joe@settoplinux.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <stdlib.h> -#include <device/pci_def.h> -#include <arch/io.h> -#include <device/pnp_def.h> -#include <console/console.h> -#include <southbridge/intel/i82801bx/i82801bx.h> -#include <northbridge/intel/i82810/raminit.h> -#include <cpu/x86/bist.h> -#include <cpu/intel/romstage.h> -#include <superio/smsc/smscsuperio/smscsuperio.h> -#include "gpio.c" -#include <lib.h> - -#define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1) - -void mainboard_romstage_entry(unsigned long bist) -{ - /* Set southbridge and Super I/O GPIOs. */ - mb_gpio_init(); - - smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - - report_bist_failure(bist); - enable_smbus(); - dump_spd_registers(); - sdram_set_registers(); - sdram_set_spd_registers(); - sdram_enable(); -} diff --git a/src/mainboard/mitac/6513wu/Kconfig b/src/mainboard/mitac/6513wu/Kconfig deleted file mode 100644 index 0266016aad..0000000000 --- a/src/mainboard/mitac/6513wu/Kconfig +++ /dev/null @@ -1,38 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -if BOARD_MITAC_6513WU - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select CPU_INTEL_SOCKET_PGA370 - select NORTHBRIDGE_INTEL_I82810 - select SOUTHBRIDGE_INTEL_I82801AX - select SUPERIO_SMSC_SMSCSUPERIO - select HAVE_PIRQ_TABLE - select BOARD_ROMSIZE_KB_512 - -config MAINBOARD_DIR - string - default mitac/6513wu - -config MAINBOARD_PART_NUMBER - string - default "6513WU" - -config IRQ_SLOT_COUNT - int - default 8 - -endif # BOARD_MITAC_6513WU diff --git a/src/mainboard/mitac/6513wu/Kconfig.name b/src/mainboard/mitac/6513wu/Kconfig.name deleted file mode 100644 index bee249ac20..0000000000 --- a/src/mainboard/mitac/6513wu/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_MITAC_6513WU - bool "6513WU" diff --git a/src/mainboard/mitac/6513wu/board_info.txt b/src/mainboard/mitac/6513wu/board_info.txt deleted file mode 100644 index 3364212a51..0000000000 --- a/src/mainboard/mitac/6513wu/board_info.txt +++ /dev/null @@ -1,4 +0,0 @@ -Category: desktop -Board URL: http://web.archive.org/web/20050313054828/http://www.mitac.com/micweb/products/tyan/6513wu/6513wu.htm -ROM package: PLCC -Flashrom support: y diff --git a/src/mainboard/mitac/6513wu/devicetree.cb b/src/mainboard/mitac/6513wu/devicetree.cb deleted file mode 100644 index 8d99df7239..0000000000 --- a/src/mainboard/mitac/6513wu/devicetree.cb +++ /dev/null @@ -1,80 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Michael Gold <mgold@ncf.ca> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -chip northbridge/intel/i82810 # Northbridge - device cpu_cluster 0 on # APIC cluster - chip cpu/intel/socket_PGA370 # CPU - device lapic 0 on end # APIC - end - end - device domain 0 on # PCI domain - device pci 0.0 on end # Graphics Memory Controller Hub (GMCH) - device pci 1.0 on end - chip southbridge/intel/i82801ax # Southbridge - register "pirqa_routing" = "0x03" - register "pirqb_routing" = "0x05" - register "pirqc_routing" = "0x09" - register "pirqd_routing" = "0x0b" - - register "ide0_enable" = "1" - register "ide1_enable" = "1" - - device pci 1e.0 on # PCI bridge - device pci 5.0 on end # Audio controller (ESS ES1988) - end - device pci 1f.0 on # ISA bridge - chip superio/smsc/smscsuperio # Super I/O (SMSC LPC47U332) - device pnp 4e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 4e.3 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 4e.4 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 4e.5 on # MIDI port (MPU-401) - io 0x60 = 0x330 - irq 0x70 = 10 - end - device pnp 4e.7 on # PS/2 keyboard / mouse - io 0x60 = 0x60 # XXX: not relocatable - io 0x62 = 0x64 # XXX: not relocatable - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt - end - device pnp 4e.9 on # Game port - io 0x60 = 0x201 - end - device pnp 4e.a on # Runtime registers - io 0x60 = 0x400 - end - device pnp 4e.b off end # SMBus - end - end - device pci 1f.1 on end # IDE - device pci 1f.2 on end # USB - device pci 1f.3 on end # SMbus - device pci 1f.5 off end # Audio controller - device pci 1f.6 off end # Modem - end - end -end diff --git a/src/mainboard/mitac/6513wu/irq_tables.c b/src/mainboard/mitac/6513wu/irq_tables.c deleted file mode 100644 index 52979bb3bf..0000000000 --- a/src/mainboard/mitac/6513wu/irq_tables.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 Michael Gold <mgold@ncf.ca> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/pirq_routing.h> - -/* - * Each of PIRQA..D can be routed to IRQ 3-7, 9-12, 14, or 15; but the - * selected IRQs can't be shared with ISA devices (Intel DS 290655-003, - * section 5.7.6). - * - * Correspondingly, the IRQs used on the Super I/O (4,6,7,10,12) are - * excluded from the masks, leaving 0xca28 (3,5,9,11,14,15). - */ - -static const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ - 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ - 0x00, /* Interrupt router bus */ - (0x1f << 3) | 0x0, /* Interrupt router dev */ - 0, /* IRQs devoted exclusively to PCI usage */ - 0x8086, /* Vendor */ - 0x7000, /* Device */ - 0, /* Miniport */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0xb6, /* Checksum (has to be set to some value that - * would give 0 after the sum of all bytes - * for this structure (including checksum). - */ - { - /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00, (0x1f << 3) | 0x0, {{0x00, 0x0000}, {0x61, 0xca28}, {0x00, 0x0000}, {0x63, 0xca28}}, 0x0, 0x0}, - {0x00, (0x1e << 3) | 0x0, {{0x60, 0xca28}, {0x61, 0xca28}, {0x62, 0xca28}, {0x63, 0xca28}}, 0x0, 0x0}, - {0x00, (0x01 << 3) | 0x0, {{0x60, 0xca28}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, - {0x01, (0x05 << 3) | 0x0, {{0x63, 0xca28}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, - {0x01, (0x08 << 3) | 0x0, {{0x60, 0xca28}, {0x61, 0xca28}, {0x62, 0xca28}, {0x63, 0xca28}}, 0x1, 0x0}, - {0x01, (0x09 << 3) | 0x0, {{0x61, 0xca28}, {0x62, 0xca28}, {0x63, 0xca28}, {0x60, 0xca28}}, 0x2, 0x0}, - {0x01, (0x0a << 3) | 0x0, {{0x62, 0xca28}, {0x63, 0xca28}, {0x60, 0xca28}, {0x61, 0xca28}}, 0x3, 0x0}, - {0x01, (0x0b << 3) | 0x0, {{0x63, 0xca28}, {0x60, 0xca28}, {0x61, 0xca28}, {0x62, 0xca28}}, 0x4, 0x0}, - } -}; - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - return copy_pirq_routing_table(addr, &intel_irq_routing_table); -} diff --git a/src/mainboard/mitac/6513wu/romstage.c b/src/mainboard/mitac/6513wu/romstage.c deleted file mode 100644 index 66989d9f20..0000000000 --- a/src/mainboard/mitac/6513wu/romstage.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 Michael Gold <mgold@ncf.ca> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <stdlib.h> -#include <device/pci_def.h> -#include <arch/io.h> -#include <device/pnp_def.h> -#include <console/console.h> -#include <southbridge/intel/i82801ax/i82801ax.h> -#include <northbridge/intel/i82810/raminit.h> -#include <delay.h> -#include <cpu/x86/bist.h> -#include <cpu/intel/romstage.h> -#include <superio/smsc/smscsuperio/smscsuperio.h> -#include <lib.h> - -#define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1) - -void mainboard_romstage_entry(unsigned long bist) -{ - smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - - report_bist_failure(bist); - enable_smbus(); - dump_spd_registers(); - sdram_set_registers(); - sdram_set_spd_registers(); - sdram_enable(); -} diff --git a/src/mainboard/mitac/Kconfig b/src/mainboard/mitac/Kconfig deleted file mode 100644 index aca84bc855..0000000000 --- a/src/mainboard/mitac/Kconfig +++ /dev/null @@ -1,30 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -if VENDOR_MITAC - -choice - prompt "Mainboard model" - -source "src/mainboard/mitac/*/Kconfig.name" - -endchoice - -source "src/mainboard/mitac/*/Kconfig" - -config MAINBOARD_VENDOR - string - default "Mitac" - -endif # VENDOR_MITAC diff --git a/src/mainboard/mitac/Kconfig.name b/src/mainboard/mitac/Kconfig.name deleted file mode 100644 index f9c1c4bbc6..0000000000 --- a/src/mainboard/mitac/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config VENDOR_MITAC - bool "Mitac" diff --git a/src/mainboard/msi/ms6178/Kconfig b/src/mainboard/msi/ms6178/Kconfig deleted file mode 100644 index c7bd464a3c..0000000000 --- a/src/mainboard/msi/ms6178/Kconfig +++ /dev/null @@ -1,43 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -if BOARD_MSI_MS_6178 - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select CPU_INTEL_SOCKET_PGA370 - select NORTHBRIDGE_INTEL_I82810 - select SOUTHBRIDGE_INTEL_I82801AX - select SUPERIO_WINBOND_W83627HF - select HAVE_PIRQ_TABLE - select BOARD_ROMSIZE_KB_512 - -config MAINBOARD_DIR - string - default msi/ms6178 - -config MAINBOARD_PART_NUMBER - string - default "MS-6178" - -config IRQ_SLOT_COUNT - int - default 4 - -# No need to override the chipset VGA_BIOS_ID. -config VGA_BIOS_FILE - string - default "i810.vga" - -endif # BOARD_MSI_MS_6178 diff --git a/src/mainboard/msi/ms6178/Kconfig.name b/src/mainboard/msi/ms6178/Kconfig.name deleted file mode 100644 index fbd0fc11a4..0000000000 --- a/src/mainboard/msi/ms6178/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_MSI_MS_6178 - bool "MS-6178" diff --git a/src/mainboard/msi/ms6178/board_info.txt b/src/mainboard/msi/ms6178/board_info.txt deleted file mode 100644 index bd5f6f7cf6..0000000000 --- a/src/mainboard/msi/ms6178/board_info.txt +++ /dev/null @@ -1,5 +0,0 @@ -Category: desktop -Board URL: http://no.msi.com/product/mb/MS-6178.html -ROM package: PLCC -ROM socketed: y -Release year: 1999 diff --git a/src/mainboard/msi/ms6178/devicetree.cb b/src/mainboard/msi/ms6178/devicetree.cb deleted file mode 100644 index 12703f5a8b..0000000000 --- a/src/mainboard/msi/ms6178/devicetree.cb +++ /dev/null @@ -1,79 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -chip northbridge/intel/i82810 # Northbridge - device cpu_cluster 0 on # APIC cluster - chip cpu/intel/socket_PGA370 # CPU - device lapic 0 on end # APIC - end - end - device domain 0 on - device pci 0.0 on end # Host bridge - device pci 1.0 on end # Onboard VGA - chip southbridge/intel/i82801ax # Southbridge - register "ide0_enable" = "1" - register "ide1_enable" = "1" - - device pci 1e.0 on end # PCI bridge - device pci 1f.0 on # ISA/LPC bridge - chip superio/winbond/w83627hf # Super I/O - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # Com2 (only header on board) - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # PS/2 keyboard/mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # Keyboard interrupt - irq 0x72 = 12 # Mouse interrupt - end - device pnp 2e.6 off end # Consumer IR (TODO) - device pnp 2e.7 on # Game port / MIDI / GPIO 1 - io 0x60 = 0x201 - io 0x62 = 0x330 - irq 0x70 = 9 - end - device pnp 2e.8 on end # GPIO 2 - device pnp 2e.9 on end # GPIO 3 - device pnp 2e.a on end # ACPI - device pnp 2e.b on # Hardware monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1f.1 on end # IDE - device pci 1f.2 on end # USB - device pci 1f.3 on end # SMBus - device pci 1f.5 on end # AC'97 audio - device pci 1f.6 on end # AC'97 modem - end - end -end diff --git a/src/mainboard/msi/ms6178/irq_tables.c b/src/mainboard/msi/ms6178/irq_tables.c deleted file mode 100644 index fae5bcf998..0000000000 --- a/src/mainboard/msi/ms6178/irq_tables.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/pirq_routing.h> - -static const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, - PIRQ_VERSION, - 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ - 0x00, /* Interrupt router bus */ - (0x1f << 3) | 0x0, /* Interrupt router device */ - 0x1c00, /* IRQs devoted exclusively to PCI usage */ - 0x8086, /* Vendor */ - 0x7000, /* Device */ - 0, /* Miniport data */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x1a, /* Checksum */ - { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x1e << 3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x1, 0x0}, - {0x00,(0x10 << 3)|0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0x0deb8}}, 0x2, 0x0}, - {0x00,(0x01 << 3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0}, - {0x00,(0x1f << 3)|0x1, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0}, - } -}; - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - return copy_pirq_routing_table(addr, &intel_irq_routing_table); -} diff --git a/src/mainboard/msi/ms6178/romstage.c b/src/mainboard/msi/ms6178/romstage.c deleted file mode 100644 index 2f1180e96f..0000000000 --- a/src/mainboard/msi/ms6178/romstage.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <device/pci_def.h> -#include <arch/io.h> -#include <device/pnp_def.h> -#include <stdlib.h> -#include <console/console.h> -#include <superio/winbond/common/winbond.h> -#include <superio/winbond/w83627hf/w83627hf.h> -#include <northbridge/intel/i82810/raminit.h> -#include <cpu/x86/bist.h> -#include <cpu/intel/romstage.h> -#include <southbridge/intel/i82801ax/i82801ax.h> -#include <lib.h> - -#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) -#define DUMMY_DEV PNP_DEV(0x2e, 0) - -void mainboard_romstage_entry(unsigned long bist) -{ - winbond_set_clksel_48(DUMMY_DEV); - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - - console_init(); - enable_smbus(); - report_bist_failure(bist); - dump_spd_registers(); - sdram_set_registers(); - sdram_set_spd_registers(); - sdram_enable(); -} diff --git a/src/mainboard/nec/Kconfig b/src/mainboard/nec/Kconfig deleted file mode 100644 index f2907356a1..0000000000 --- a/src/mainboard/nec/Kconfig +++ /dev/null @@ -1,30 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -if VENDOR_NEC - -choice - prompt "Mainboard model" - -source "src/mainboard/nec/*/Kconfig.name" - -endchoice - -source "src/mainboard/nec/*/Kconfig" - -config MAINBOARD_VENDOR - string - default "NEC" - -endif # VENDOR_NEC diff --git a/src/mainboard/nec/Kconfig.name b/src/mainboard/nec/Kconfig.name deleted file mode 100644 index 5f4f89212c..0000000000 --- a/src/mainboard/nec/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config VENDOR_NEC - bool "NEC" diff --git a/src/mainboard/nec/powermate2000/Kconfig b/src/mainboard/nec/powermate2000/Kconfig deleted file mode 100644 index fe546faca4..0000000000 --- a/src/mainboard/nec/powermate2000/Kconfig +++ /dev/null @@ -1,38 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -if BOARD_NEC_POWERMATE_2000 - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select CPU_INTEL_SOCKET_PGA370 - select NORTHBRIDGE_INTEL_I82810 - select SOUTHBRIDGE_INTEL_I82801AX - select SUPERIO_SMSC_SMSCSUPERIO - select HAVE_PIRQ_TABLE - select BOARD_ROMSIZE_KB_512 - -config MAINBOARD_DIR - string - default nec/powermate2000 - -config MAINBOARD_PART_NUMBER - string - default "PowerMate 2000" - -config IRQ_SLOT_COUNT - int - default 5 - -endif # BOARD_NEC_POWERMATE_2000 diff --git a/src/mainboard/nec/powermate2000/Kconfig.name b/src/mainboard/nec/powermate2000/Kconfig.name deleted file mode 100644 index 3f46dceba2..0000000000 --- a/src/mainboard/nec/powermate2000/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_NEC_POWERMATE_2000 - bool "PowerMate 2000" diff --git a/src/mainboard/nec/powermate2000/board_info.txt b/src/mainboard/nec/powermate2000/board_info.txt deleted file mode 100644 index 50a4b2a6d9..0000000000 --- a/src/mainboard/nec/powermate2000/board_info.txt +++ /dev/null @@ -1,4 +0,0 @@ -Category: desktop -Board URL: http://support.necam.com/mobilesolutions/hardware/Desktops/pm2000/celeron/ -ROM socketed: n -Flashrom support: y diff --git a/src/mainboard/nec/powermate2000/devicetree.cb b/src/mainboard/nec/powermate2000/devicetree.cb deleted file mode 100644 index a3f164e968..0000000000 --- a/src/mainboard/nec/powermate2000/devicetree.cb +++ /dev/null @@ -1,53 +0,0 @@ -chip northbridge/intel/i82810 # Northbridge - device cpu_cluster 0 on # APIC cluster - chip cpu/intel/socket_PGA370 # CPU - device lapic 0 on end # APIC - end - end - device domain 0 on - device pci 0.0 on end # Host bridge - device pci 1.0 off end # Onboard video - chip southbridge/intel/i82801ax # Southbridge - register "ide0_enable" = "1" - register "ide1_enable" = "1" - - device pci 1e.0 on end # PCI bridge - device pci 1f.0 on # ISA/LPC bridge - chip superio/smsc/smscsuperio # Super I/O (SMSC LPC47B27x) - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.3 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 2e.4 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.5 off end # Com2 (N/A) - device pnp 2e.7 on # PS/2 keyboard - irq 0x70 = 1 - irq 0x72 = 0 - end - device pnp 2e.9 off end # Game port (N/A) - device pnp 2e.a on # Power-management events (PME) - io 0x60 = 0x800 - end - device pnp 2e.b on # MIDI port - io 0x60 = 0x330 - irq 0x70 = 5 - end - end - end - device pci 1f.1 on end # IDE - device pci 1f.2 on end # USB - device pci 1f.3 on end # SMBus - device pci 1f.5 on end # AC'97 audio - device pci 1f.6 off end # AC'97 modem (N/A) - end - end -end diff --git a/src/mainboard/nec/powermate2000/irq_tables.c b/src/mainboard/nec/powermate2000/irq_tables.c deleted file mode 100644 index 6dde889591..0000000000 --- a/src/mainboard/nec/powermate2000/irq_tables.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/pirq_routing.h> - -static const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, - PIRQ_VERSION, - 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ - 0x00, /* Interrupt router bus */ - (0x1f << 3) | 0x0, /* Interrupt router device */ - 0, /* IRQs devoted exclusively to PCI usage */ - 0x8086, /* Vendor */ - 0x122e, /* Device */ - 0, /* Miniport data */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x6e, /* Checksum */ - { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00, (0x1e << 3) | 0x0, {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}}, 0x0, 0x0}, - {0x01, (0x03 << 3) | 0x0, {{0x61, 0xdef8}, {0x62, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0}, - {0x01, (0x04 << 3) | 0x0, {{0x62, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0}, - {0x00, (0x1f << 3) | 0x0, {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}}, 0x0, 0x0}, - {0x00, (0x01 << 3) | 0x0, {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0}, - } -}; - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - return copy_pirq_routing_table(addr, &intel_irq_routing_table); -} diff --git a/src/mainboard/nec/powermate2000/romstage.c b/src/mainboard/nec/powermate2000/romstage.c deleted file mode 100644 index 6e6358023f..0000000000 --- a/src/mainboard/nec/powermate2000/romstage.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <device/pci_def.h> -#include <arch/io.h> -#include <device/pnp_def.h> -#include <stdlib.h> -#include <console/console.h> -#include <superio/smsc/smscsuperio/smscsuperio.h> -#include <northbridge/intel/i82810/raminit.h> -#include <cpu/x86/bist.h> -#include <cpu/intel/romstage.h> -#include <southbridge/intel/i82801ax/i82801ax.h> -#include <lib.h> - -#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) - -void mainboard_romstage_entry(unsigned long bist) -{ - smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - enable_smbus(); - report_bist_failure(bist); - dump_spd_registers(); - sdram_set_registers(); - sdram_set_spd_registers(); - sdram_enable(); -} diff --git a/src/northbridge/intel/i82810/Kconfig b/src/northbridge/intel/i82810/Kconfig deleted file mode 100644 index 7d8c46b47c..0000000000 --- a/src/northbridge/intel/i82810/Kconfig +++ /dev/null @@ -1,47 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -config NORTHBRIDGE_INTEL_I82810 - bool - select NO_MMCONF_SUPPORT - select HAVE_DEBUG_RAM_SETUP - select LATE_CBMEM_INIT - select UDELAY_IO - -choice - prompt "Onboard graphics" - default I810_VIDEO_MB_1MB - depends on NORTHBRIDGE_INTEL_I82810 - -config I810_VIDEO_MB_OFF - bool "Disabled, 0KB" -config I810_VIDEO_MB_512KB - bool "Enabled, 512KB" -config I810_VIDEO_MB_1MB - bool "Enabled, 1MB" - -endchoice - -config VIDEO_MB - int - default 0 if I810_VIDEO_MB_OFF - default 512 if I810_VIDEO_MB_512KB - default 1 if I810_VIDEO_MB_1MB - depends on NORTHBRIDGE_INTEL_I82810 - -config VGA_BIOS_ID - string - default "8086,7121" - depends on NORTHBRIDGE_INTEL_I82810 diff --git a/src/northbridge/intel/i82810/Makefile.inc b/src/northbridge/intel/i82810/Makefile.inc deleted file mode 100644 index 474de8caeb..0000000000 --- a/src/northbridge/intel/i82810/Makefile.inc +++ /dev/null @@ -1,24 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I82810),y) - -ramstage-y += northbridge.c - -romstage-y += raminit.c -romstage-y += debug.c - -endif diff --git a/src/northbridge/intel/i82810/debug.c b/src/northbridge/intel/i82810/debug.c deleted file mode 100644 index d81713859c..0000000000 --- a/src/northbridge/intel/i82810/debug.c +++ /dev/null @@ -1,52 +0,0 @@ -#include <console/console.h> -#include <arch/io.h> -#include <spd.h> -#include "raminit.h" -#include <spd.h> -#include <console/console.h> - -#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) -void dump_spd_registers(void) -{ - int i; - printk(BIOS_DEBUG, "\n"); - for (i = 0; i < DIMM_SOCKETS; i++) { - unsigned device; - device = DIMM0 + i; - if (device) { - int j; - printk(BIOS_DEBUG, "DIMM %d: %02x", i, device); - for (j = 0; j < 256; j++) { - int status; - unsigned char byte; - if ((j & 0xf) == 0) { - printk(BIOS_DEBUG, "\n%02x: ", j); - } - status = smbus_read_byte(device, j); - if (status < 0) { - printk(BIOS_DEBUG, "bad device\n"); - break; - } - byte = status & 0xff; - printk(BIOS_DEBUG, "%02x ", byte); - } - printk(BIOS_DEBUG, "\n"); - } - } -} - -void dump_pci_device(unsigned dev) -{ - int i; - printk(BIOS_DEBUG, "PCI: %02x:%02x.%02x\n", (dev >> 20) & 0xff, (dev >> 15) & 0x1f, (dev >> 12) & 7); - - for (i = 0; i <= 255; i++) { - unsigned char val; - val = pci_read_config8(dev, i); - if ((i & 0x0f) == 0) - printk(BIOS_DEBUG, "%02x: %02x", i, val); - if ((i & 0x0f) == 0x0f) - printk(BIOS_DEBUG, "\n"); - } -} -#endif diff --git a/src/northbridge/intel/i82810/i82810.h b/src/northbridge/intel/i82810/i82810.h deleted file mode 100644 index 28a5ca1979..0000000000 --- a/src/northbridge/intel/i82810/i82810.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef NORTHBRIDGE_INTEL_I82810_I82810_H -#define NORTHBRIDGE_INTEL_I82810_I82810_H - -/* - * Datasheet: - * - Name: Intel 810 Chipset: - * 82810/82810-DC100 Graphics and Memory Controller Hub (GMCH) - * - URL: http://www.intel.com/design/chipsets/datashts/290656.htm - * - PDF: ftp://download.intel.com/design/chipsets/datashts/29065602.pdf - * - Order Number: 290656-002 - */ - -/* - * PCI Configuration Registers. - * - * Any addresses between 0x50 and 0xff not listed below are reserved and - * should not be touched. - */ - -#define GMCHCFG 0x50 /* GMCH Configuration */ -#define PAMR 0x51 /* Programmable Attributes */ -#define DRP 0x52 /* DRAM Row Population */ -#define DRAMT 0x53 /* DRAM Timing */ -#define FDHC 0x58 /* Fixed DRAM Hole Control */ -#define SMRAM 0x70 /* System Management RAM Control */ -#define MISSC 0x72 /* Miscellaneous Control */ -#define MISSC2 0x80 /* Miscellaneous Control 2 */ -#define BUFF_SC 0x92 /* System Memory Buffer Strength Control */ - -int smbus_read_byte(u8 device, u8 address); - -#endif diff --git a/src/northbridge/intel/i82810/northbridge.c b/src/northbridge/intel/i82810/northbridge.c deleted file mode 100644 index 2274c0f5e2..0000000000 --- a/src/northbridge/intel/i82810/northbridge.c +++ /dev/null @@ -1,161 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com> - * Copyright (C) 2010 Joseph Smith <joe@settoplinux.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <arch/io.h> -#include <stdint.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <stdlib.h> -#include <string.h> -#include <cbmem.h> -#include <cpu/cpu.h> -#include "northbridge.h" -#include "i82810.h" - -static void northbridge_init(device_t dev) -{ - printk(BIOS_SPEW, "Northbridge init\n"); -} - -static struct device_operations northbridge_operations = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = northbridge_init, - .enable = 0, - .ops_pci = 0, -}; - -/* Intel 82810/82810-DC100 */ -static const struct pci_driver i810_northbridge_driver __pci_driver = { - .ops = &northbridge_operations, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x7120, -}; - -/* Intel 82810E */ -static const struct pci_driver i810e_northbridge_driver __pci_driver = { - .ops = &northbridge_operations, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x7124, -}; - -/* Table which returns the RAM size in MB when fed the DRP[7:4] or [3:0] value. - * Note that 2 is a value which the DRP should never be programmed to. - * Some size values appear twice, due to single-sided vs dual-sided banks. - */ -static int translate_i82810_to_mb[] = { -/* DRP 0 1 (2) 3 4 5 6 7 8 9 A B C D E F */ -/* MB */0, 8, 0, 16, 16, 24, 32, 32, 48, 64, 64, 96, 128, 128, 192, 256, -}; - -static void pci_domain_set_resources(device_t dev) -{ - device_t mc_dev; - int igd_memory = 0; - uint64_t uma_memory_base = 0, uma_memory_size = 0; - - mc_dev = dev->link_list->children; - if (!mc_dev) - return; - - unsigned long tomk, tomk_stolen; - int idx, drp_value; - u8 reg8; - - reg8 = pci_read_config8(mc_dev, SMRAM); - reg8 &= 0xc0; - - switch (reg8) { - case 0xc0: - igd_memory = 1024; - printk(BIOS_DEBUG, "%dKB IGD UMA\n", igd_memory); - break; - case 0x80: - igd_memory = 512; - printk(BIOS_DEBUG, "%dKB IGD UMA\n", igd_memory); - break; - default: - igd_memory = 0; - printk(BIOS_DEBUG, "No IGD UMA Memory\n"); - break; - } - - /* Get the value for DIMM 0 and translate it to MB. */ - drp_value = pci_read_config8(mc_dev, DRP); - tomk = (unsigned long)(translate_i82810_to_mb[drp_value & 0x0f]); - /* Get the value for DIMM 1 and translate it to MB. */ - drp_value = drp_value >> 4; - tomk += (unsigned long)(translate_i82810_to_mb[drp_value]); - /* Convert tomk from MB to KB. */ - tomk = tomk << 10; - tomk_stolen = tomk - igd_memory; - - /* For reserving UMA memory in the memory map */ - uma_memory_base = tomk_stolen * 1024ULL; - uma_memory_size = igd_memory * 1024ULL; - printk(BIOS_DEBUG, "Available memory: %ldKB\n", tomk_stolen); - - /* Report the memory regions. */ - idx = 10; - ram_resource(dev, idx++, 0, 640); - ram_resource(dev, idx++, 768, tomk - 768); - uma_resource(dev, idx++, uma_memory_base >> 10, uma_memory_size >> 10); - - set_late_cbmem_top(tomk_stolen * 1024); - - assign_resources(dev->link_list); -} - -static struct device_operations pci_domain_ops = { - .read_resources = pci_domain_read_resources, - .set_resources = pci_domain_set_resources, - .enable_resources = NULL, - .init = NULL, - .scan_bus = pci_domain_scan_bus, - .ops_pci_bus = pci_bus_default_ops, -}; - -static void cpu_bus_init(device_t dev) -{ - initialize_cpus(dev->link_list); -} - -static struct device_operations cpu_bus_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, - .init = cpu_bus_init, - .scan_bus = 0, -}; - -static void enable_dev(struct device *dev) -{ - /* Set the operations if it is a special bus type */ - if (dev->path.type == DEVICE_PATH_DOMAIN) { - dev->ops = &pci_domain_ops; - } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { - dev->ops = &cpu_bus_ops; - } -} - -struct chip_operations northbridge_intel_i82810_ops = { - CHIP_NAME("Intel 82810 Northbridge") - .enable_dev = enable_dev, -}; diff --git a/src/northbridge/intel/i82810/northbridge.h b/src/northbridge/intel/i82810/northbridge.h deleted file mode 100644 index a9b26d5cf9..0000000000 --- a/src/northbridge/intel/i82810/northbridge.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef NORTHBRIDGE_INTEL_I82810_NORTHBRIDGE_H -#define NORTHBRIDGE_INTEL_I82810_NORTHBRIDGE_H - -extern unsigned int i82810_scan_root_bus(device_t root, unsigned int max); - -#endif /* NORTHBRIDGE_INTEL_I82810_NORTHBRIDGE_H */ diff --git a/src/northbridge/intel/i82810/raminit.c b/src/northbridge/intel/i82810/raminit.c deleted file mode 100644 index 6fe4fb590a..0000000000 --- a/src/northbridge/intel/i82810/raminit.c +++ /dev/null @@ -1,463 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 Uwe Hermann <uwe@hermann-uwe.de> - * Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com> - * Copyright (C) 2008-2009 Elia Yehuda <z4ziggy@gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <spd.h> -#include <delay.h> -#include <stdint.h> -#include <arch/io.h> -#include <device/pci_def.h> -#include <console/console.h> -#include "i82810.h" -#include "raminit.h" - -/*----------------------------------------------------------------------------- -Macros and definitions. ------------------------------------------------------------------------------*/ - -/* Debugging macros. */ -#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) -#define PRINT_DEBUG(x...) printk(BIOS_DEBUG, x) -#define DUMPNORTH() dump_pci_device(PCI_DEV(0, 0, 0)) -#else -#define PRINT_DEBUG(x...) -#define DUMPNORTH() -#endif - -/* DRAMT[7:5] - SDRAM Mode Select (SMS). */ -#define RAM_COMMAND_SELF_REFRESH 0x0 /* Disable refresh */ -#define RAM_COMMAND_NORMAL 0x1 /* Refresh: 15.6/11.7us for 100/133MHz */ -#define RAM_COMMAND_NORMAL_FR 0x2 /* Refresh: 7.8/5.85us for 100/133MHz */ -#define RAM_COMMAND_NOP 0x4 /* NOP command */ -#define RAM_COMMAND_PRECHARGE 0x5 /* All bank precharge */ -#define RAM_COMMAND_MRS 0x6 /* Mode register set */ -#define RAM_COMMAND_CBR 0x7 /* CBR */ - -/* - * This table is used to translate the value read from SPD Byte 31 to a value - * the northbridge can understand in DRP, aka Rx52[7:4], [3:0]. Where most - * northbridges have some sort of simple calculation that can be done for this, - * I haven't yet figured out one for this northbridge. Until someone does, - * this table is necessary. - */ -static const u8 translate_spd_to_i82810[] = { - /* Note: 4MB sizes are not supported, so dual-sided DIMMs with a 4MB - * side can't be either, at least for now. - */ - /* TODO: For above case, only use the other side if > 4MB, and get some - * of these DIMMs to test it with. Same for unsupported 128/x sizes. - */ - - /* SPD Byte 31 Memory Size [Side 1/2] */ - 0xff, /* 0x01 No memory */ - 0xff, /* 0x01 4/0 */ - 0x01, /* 0x02 8/0 */ - 0xff, /* 0x03 8/4 */ - 0x04, /* 0x04 16/0 or 16 */ - 0xff, /* 0x05 16/4 */ - 0x05, /* 0x06 16/8 */ - 0xff, /* 0x07 Invalid */ - 0x07, /* 0x08 32/0 or 32 */ - 0xff, /* 0x09 32/4 */ - 0xff, /* 0x0A 32/8 */ - 0xff, /* 0x0B Invalid */ - 0x08, /* 0x0C 32/16 */ - 0xff, 0xff, 0xff, /* 0x0D-0F Invalid */ - 0x0a, /* 0x10 64/0 or 64 */ - 0xff, /* 0x11 64/4 */ - 0xff, /* 0x12 64/8 */ - 0xff, /* 0x13 Invalid */ - 0xff, /* 0x14 64/16 */ - 0xff, 0xff, 0xff, /* 0x15-17 Invalid */ - 0x0b, /* 0x18 64/32 */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0x19-1f Invalid */ - 0x0d, /* 0x20 128/0 or 128 */ - /* These configurations are not supported by the i810 */ - 0xff, /* 0x21 128/4 */ - 0xff, /* 0x22 128/8 */ - 0xff, /* 0x23 Invalid */ - 0xff, /* 0x24 128/16 */ - 0xff, 0xff, 0xff, /* 0x25-27 Invalid */ - 0xff, /* 0x28 128/32 */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0x29-2f Invalid */ - 0x0e, /* 0x30 128/64 */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, /* 0x31-3f Invalid */ - 0x0f, /* 0x40 256/0 or 256 */ - /* Anything larger is not supported by the 82810. */ -}; - -/* - * Table which returns the RAM size in MB when fed the DRP[7:4] or [3:0] value. - * Note that 2 is a value which the DRP should never be programmed to. - * Some size values appear twice, due to single-sided vs dual-sided banks. - */ -static const u16 translate_i82810_to_mb[] = { -/* DRP 0 1 (2) 3 4 5 6 7 8 9 A B C D E F */ -/* MB */0, 8, 0, 16, 16, 24, 32, 32, 48, 64, 64, 96, 128, 128, 192, 256, -}; - -/* Size of bank#0 for dual-sided DIMMs */ -static const u8 translate_i82810_to_bank[] = { -/* DRP 0 1 (2) 3 4 5 6 7 8 9 A B C D E F */ -/* MB */0, 0, 0, 8, 0, 16, 16, 0, 32, 32, 0, 64, 64, 0, 128, 128, -}; - -struct dimm_info { - u8 ds; /* dual-sided */ - u8 ss; /* single-sided */ - u8 size; -}; - -/*----------------------------------------------------------------------------- -SDRAM configuration functions. ------------------------------------------------------------------------------*/ - -/** - * Send the specified RAM command to all DIMMs. - * - * @param command The RAM command to send to the DIMM(s). - */ -static void do_ram_command(u8 command) -{ - u32 *addr, addr_offset; - u16 dimm_size, dimm_start, dimm_bank; - u8 reg8, drp; - int i, caslatency; - - /* Configure the RAM command. */ - reg8 = pci_read_config8(PCI_DEV(0, 0, 0), DRAMT); - reg8 &= 0x1f; /* Clear bits 7-5. */ - reg8 |= command << 5; - pci_write_config8(PCI_DEV(0, 0, 0), DRAMT, reg8); - - /* - * RAM_COMMAND_NORMAL affects only the memory controller and - * doesn't need to be "sent" to the DIMMs. - */ - if (command == RAM_COMMAND_NORMAL) - return; - - dimm_start = 0; - for (i = 0; i < DIMM_SOCKETS; i++) { - /* - * Calculate the address offset where we need to "send" the - * DIMM command to. For most commands the offset is 0, only - * RAM_COMMAND_MRS needs special values, see below. - * The final address offset bits depend on three things: - * - * (1) Some hardcoded values specified in the datasheet. - * (2) Which CAS latency we will use/set. This is the SMAA[4] - * bit, which is 1 for CL3, and 0 for CL2. The bitstring - * so far has the form '00000001X1010', X being SMAA[4]. - * (3) The DIMM to which we want to send the command. For - * DIMM0 no special handling is needed, but for DIMM1 we - * must invert the four bits SMAA[7:4] (see datasheet). - * - * Finally, the bitstring has to be shifted 3 bits to the left. - * See i810 datasheet pages 43, 85, and 86 for details. - */ - addr_offset = 0; - caslatency = 3; /* TODO: Dynamically get CAS latency later. */ - if (i == 0 && command == RAM_COMMAND_MRS && caslatency == 3) - addr_offset = 0x1d0; /* DIMM0, CL3, 0000111010000 */ - if (i == 1 && command == RAM_COMMAND_MRS && caslatency == 3) - addr_offset = 0x650; /* DIMM1, CL3, 0011001010000 */ - if (i == 0 && command == RAM_COMMAND_MRS && caslatency == 2) - addr_offset = 0x150; /* DIMM0, CL2, 0000101010000 */ - if (i == 1 && command == RAM_COMMAND_MRS && caslatency == 2) - addr_offset = 0x1a0; /* DIMM1, CL2, 0000110100000 */ - - drp = pci_read_config8(PCI_DEV(0, 0, 0), DRP); - drp = (drp >> (i * 4)) & 0x0f; - - dimm_size = translate_i82810_to_mb[drp]; - if (dimm_size) { - addr = (u32 *)((dimm_start * 1024 * 1024) + addr_offset); - PRINT_DEBUG(" Sending RAM command 0x%02x to 0x%p\n", reg8, addr); - read32(addr); - } - - dimm_bank = translate_i82810_to_bank[drp]; - if (dimm_bank) { - addr = (u32 *)(((dimm_start + dimm_bank) * 1024 * 1024) + addr_offset); - PRINT_DEBUG(" Sending RAM command 0x%02x to 0x%p\n", reg8, addr); - read32(addr); - } - - dimm_start += dimm_size; - } -} - -/*----------------------------------------------------------------------------- -DIMM-independent configuration functions. ------------------------------------------------------------------------------*/ - -/* - * Set DRP - DRAM Row Population Register (Device 0). - */ -static void spd_set_dram_size(void) -{ - /* The variables drp and dimm_size have to be ints since all the - * SMBus-related functions return ints, and its just easier this way. - */ - int i, drp, dimm_size; - - drp = 0x00; - - for (i = 0; i < DIMM_SOCKETS; i++) { - /* First check if a DIMM is actually present. */ - if (smbus_read_byte(DIMM0 + i, 2) == 4) { - printk(BIOS_DEBUG, "Found DIMM in slot %d\n", i); - - dimm_size = smbus_read_byte(DIMM0 + i, 31); - - printk(BIOS_DEBUG, "DIMM is %dMB\n", dimm_size * 4); - - /* The i810 can't handle DIMMs larger than 128MB per - * side. This will fail if the DIMM uses a - * non-supported DRAM tech, and can't be used until - * buffers are done dynamically. - * Note: the factory BIOS just dies if it spots this :D - */ - if (dimm_size > 32) { - printk(BIOS_ERR, "DIMM row sizes larger than 128MB not" - "supported on i810\n"); - printk - (BIOS_ERR, "Attempting to treat as 128MB DIMM\n"); - dimm_size = 32; - } else if (dimm_size < 0) { - /* On smbus error, set DIMM size to 0 */ - printk(BIOS_ERR, "Error reading DIMM size\n"); - dimm_size = 0; - } - - if (dimm_size > 0) { - /* This array is provided in raminit.h, because it got - * extremely messy. The above way is cleaner, but - * doesn't support any asymmetrical/odd configurations. - */ - dimm_size = translate_spd_to_i82810[dimm_size]; - - printk(BIOS_DEBUG, "After translation, dimm_size is %d\n", - dimm_size); - - /* If the DIMM is dual-sided, the DRP value is +2 */ - /* TODO: Figure out asymmetrical configurations. */ - if ((smbus_read_byte(DIMM0 + i, 127) | 0xf) == 0xff) { - printk(BIOS_DEBUG, "DIMM is dual-sided\n"); - dimm_size += 2; - } - } - } else { - printk(BIOS_DEBUG, "No DIMM found in slot %d\n", i); - - /* If there's no DIMM in the slot, set value to 0. */ - dimm_size = 0x00; - } - - /* Put in dimm_size to reflect the current DIMM. */ - drp |= dimm_size << (i * 4); - } - - printk(BIOS_DEBUG, "DRP calculated to 0x%02x\n", drp); - - pci_write_config8(PCI_DEV(0, 0, 0), DRP, drp); -} - -static void set_dram_timing(void) -{ - /* TODO, for now using default, hopefully safe values. */ - // pci_write_config8(PCI_DEV(0, 0, 0), DRAMT, 0x00); -} - -/* - * TODO: BUFF_SC needs to be set according to the DRAM tech (x8, x16, - * or x32), but the datasheet doesn't list all the details. Currently, it - * needs to be pulled from the output of 'lspci -xxx Rx92'. - * - * Common results (tested on actual hardware) are: - * - * (DRP: c = 128MB dual sided, d = 128MB single sided, f = 256MB dual sided) - * - * BUFF_SC TOM DRP DIMM0 DIMM1 - * ---------------------------------------------------------------------------- - * 0x3356 128MB 0x0c 128MB dual-sided - - * 0xcc56 128MB 0xc0 - 128MB dual-sided - * 0x77da 128MB 0x0d 128MB single-sided - - * 0xddda 128MB 0xd0 - 128MB single-sided - * 0x0001 256MB 0xcc 128MB dual-sided 128MB dual-sided - * 0x55c6 256MB 0xdd 128MB single-sided 128MB single-sided - * 0x4445 256MB 0xcd 128MB single-sided 128MB dual-sided - * 0x1145 256MB 0xdc 128MB dual-sided 128MB single-sided - * 0x3356 256MB 0x0f 256MB dual-sided - - * 0xcc56 256MB 0xf0 - 256MB dual-sided - * 0x0001 384MB 0xcf 256MB dual-sided 128MB dual-sided - * 0x0001 384MB 0xfc 128MB dual-sided 256MB dual-sided - * 0x1145 384MB 0xdf 256MB dual-sided 128MB single-sided - * 0x4445 384MB 0xfd 128MB single-sided 256MB dual-sided - * 0x0001 512MB 0xff 256MB dual-sided 256MB dual-sided - * - * See also: - * https://www.coreboot.org/pipermail/coreboot/2009-May/047966.html - */ -static void set_dram_buffer_strength(void) -{ - struct dimm_info d0, d1; - u16 buff_sc; - - /* Check first slot. */ - d0.size = d0.ds = d0.ss = 0; - if (smbus_read_byte(DIMM0, SPD_MEMORY_TYPE) == SPD_MEMORY_TYPE_SDRAM) { - d0.size = smbus_read_byte(DIMM0, SPD_BANK_DENSITY); - d0.ds = smbus_read_byte(DIMM0, SPD_NUM_DIMM_BANKS) > 1; - d0.ss = !d0.ds; - } - - /* Check second slot. */ - d1.size = d1.ds = d1.ss = 0; - if (smbus_read_byte(DIMM0 + 1, SPD_MEMORY_TYPE) - == SPD_MEMORY_TYPE_SDRAM) { - d1.size = smbus_read_byte(DIMM0 + 1, SPD_BANK_DENSITY); - d1.ds = smbus_read_byte(DIMM0 + 1, SPD_NUM_DIMM_BANKS) > 1; - d1.ss = !d1.ds; - } - - buff_sc = 0; - - /* Tame the beast... */ - if ((d0.ds && d1.ds) || (d0.ds && d1.ss) || (d0.ss && d1.ds)) - buff_sc |= 1; - if ((d0.size && !d1.size) || (!d0.size && d1.size) || (d0.ss && d1.ss)) - buff_sc |= 1 << 1; - if ((d0.ds && !d1.size) || (!d0.size && d1.ds) || (d0.ss && d1.ss) - || (d0.ds && d1.ss) || (d0.ss && d1.ds)) - buff_sc |= 1 << 2; - if ((d0.ss && !d1.size) || (!d0.size && d1.ss)) - buff_sc |= 1 << 3; - if ((d0.size && !d1.size) || (!d0.size && d1.size)) - buff_sc |= 1 << 4; - if ((d0.ds && !d1.size) || (!d0.size && d1.ds) || (d0.ds && d1.ss) - || (d0.ss && d1.ds)) - buff_sc |= 1 << 6; - if ((d0.ss && !d1.size) || (!d0.size && d1.ss) || (d0.ss && d1.ss)) - buff_sc |= 3 << 6; - if ((!d0.size && d1.ss) || (d0.ds && d1.ss) || (d0.ss && d1.ss)) - buff_sc |= 1 << 8; - if (d0.size && !d1.size) - buff_sc |= 3 << 8; - if ((d0.ss && !d1.size) || (d0.ss && d1.ss) || (d0.ss && d1.ds)) - buff_sc |= 1 << 10; - if (!d0.size && d1.size) - buff_sc |= 3 << 10; - if ((d0.size && !d1.size) || (d0.ss && !d1.size) || (!d0.size && d1.ss) - || (d0.ss && d1.ss) || (d0.ds && d1.ss)) - buff_sc |= 1 << 12; - if (d0.size && !d1.size) - buff_sc |= 1 << 13; - if ((!d0.size && d1.size) || (d0.ss && !d1.size) || (d0.ss && d1.ss) - || (d0.ss && d1.ds)) - buff_sc |= 1 << 14; - if (!d0.size && d1.size) - buff_sc |= 1 << 15; - - printk(BIOS_DEBUG, "BUFF_SC calculated to 0x%04x\n", buff_sc); - - pci_write_config16(PCI_DEV(0, 0, 0), BUFF_SC, buff_sc); -} - -/*----------------------------------------------------------------------------- -Public interface. ------------------------------------------------------------------------------*/ - -void sdram_set_registers(void) -{ - u8 reg8; - u16 did; - - did = pci_read_config16(PCI_DEV(0, 0, 0), PCI_DEVICE_ID); - - /* Ideally, this should be R/W for as many ranges as possible. */ - pci_write_config8(PCI_DEV(0, 0, 0), PAMR, 0xff); - - /* Set size for onboard-VGA framebuffer. */ - reg8 = pci_read_config8(PCI_DEV(0, 0, 0), SMRAM); - reg8 &= 0x3f; /* Disable graphics (for now). */ -#if CONFIG_VIDEO_MB - if (CONFIG_VIDEO_MB == 512) - reg8 |= (1 << 7); /* Enable graphics (512KB RAM). */ - else if (CONFIG_VIDEO_MB == 1) - reg8 |= (1 << 7) | (1 << 6); /* Enable graphics (1MB RAM). */ -#endif - pci_write_config8(PCI_DEV(0, 0, 0), SMRAM, reg8); - - /* MISSC2: Bits 1, 2, 6, 7 must be set for VGA (see datasheet). */ - reg8 = pci_read_config8(PCI_DEV(0, 0, 0), MISSC2); - reg8 |= (1 << 1); /* Instruction Parser Unit-Level Clock Gating */ - reg8 |= (1 << 2); /* Palette Load Select */ - if (did == 0x7124) { - /* Bits 6 and 7 are only available on 82810E (not 82810). */ - reg8 |= (1 << 6); /* Text Immediate Blit */ - reg8 |= (1 << 7); /* Must be 1 as per datasheet. */ - } - pci_write_config8(PCI_DEV(0, 0, 0), MISSC2, reg8); -} - -void sdram_set_spd_registers(void) -{ - spd_set_dram_size(); - set_dram_buffer_strength(); - set_dram_timing(); -} - -/** - * Enable SDRAM. - */ -void sdram_enable(void) -{ - int i; - - /* 1. Apply NOP. */ - PRINT_DEBUG("RAM Enable 1: Apply NOP\n"); - do_ram_command(RAM_COMMAND_NOP); - udelay(200); - - /* 2. Precharge all. Wait tRP. */ - PRINT_DEBUG("RAM Enable 2: Precharge all\n"); - do_ram_command(RAM_COMMAND_PRECHARGE); - udelay(1); - - /* 3. Perform 8 refresh cycles. Wait tRC each time. */ - PRINT_DEBUG("RAM Enable 3: CBR\n"); - for (i = 0; i < 8; i++) { - do_ram_command(RAM_COMMAND_CBR); - udelay(1); - } - - /* 4. Mode register set. Wait two memory cycles. */ - PRINT_DEBUG("RAM Enable 4: Mode register set\n"); - do_ram_command(RAM_COMMAND_MRS); - udelay(2); - - /* 5. Normal operation (enables refresh at 15.6usec). */ - PRINT_DEBUG("RAM Enable 5: Normal operation\n"); - do_ram_command(RAM_COMMAND_NORMAL); - udelay(1); - - PRINT_DEBUG("Northbridge following SDRAM init:\n"); - DUMPNORTH(); -} diff --git a/src/northbridge/intel/i82810/raminit.h b/src/northbridge/intel/i82810/raminit.h deleted file mode 100644 index 6b9d175d88..0000000000 --- a/src/northbridge/intel/i82810/raminit.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef NORTHBRIDGE_INTEL_I82810_RAMINIT_H -#define NORTHBRIDGE_INTEL_I82810_RAMINIT_H - -/* The 82810 supports max. 2 dual-sided DIMMs. */ -#define DIMM_SOCKETS 2 - -/* Function prototypes. */ -void sdram_set_registers(void); -void sdram_set_spd_registers(void); -void sdram_enable(void); - -/* Debug */ -#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) -void dump_spd_registers(void); -void dump_pci_device(unsigned dev); -#else -#define dump_spd_registers() -#endif -#endif |