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authorDerek Basehore <dbasehore@chromium.org>2016-06-17 23:29:18 -0700
committerMartin Roth <martinroth@google.com>2016-07-15 00:37:28 +0200
commit5282fe62d47a3359373d747cd093e920fe429338 (patch)
tree540484aae2592d86bd0ecfb62e9959a022a43672
parentf3b3ccfe7327232d5e3cc082a0176ae7230e0b6c (diff)
downloadcoreboot-5282fe62d47a3359373d747cd093e920fe429338.tar.xz
rockchip/rk3399: Change copy_to_reg arg type
This changes the src arg for copy_to_reg to a const u32 * instead of a u32 * in sdram.c. BRANCH=none BUG=none TEST=emerge-gru coreboot Change-Id: I80f49258b2f8102f0d988fec85b8038a00e18a34 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: e0342e5c0181bf65ae78aa9518b0d6bd6cb1d5ec Original-Change-Id: I362727f1dbe6726bf3240f9219c394786162a1a0 Original-Signed-off-by: Derek Basehore <dbasehore@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/354163 Original-Reviewed-by: Martin Roth <martinroth@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15656 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
-rw-r--r--src/soc/rockchip/rk3399/sdram.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/rockchip/rk3399/sdram.c b/src/soc/rockchip/rk3399/sdram.c
index 1644969979..47fa09819d 100644
--- a/src/soc/rockchip/rk3399/sdram.c
+++ b/src/soc/rockchip/rk3399/sdram.c
@@ -100,7 +100,7 @@ static struct rk3399_msch_regs * const rk3399_msch[2] = {
#define PHY_DRV_ODT_40 (0xe)
#define PHY_DRV_ODT_34_3 (0xf)
-static void copy_to_reg(u32 *dest, u32 *src, u32 n)
+static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
{
int i;
@@ -400,8 +400,8 @@ static void pctl_cfg(u32 channel,
u32 *denali_ctl = rk3399_ddr_pctl[channel]->denali_ctl;
u32 *denali_pi = rk3399_ddr_pi[channel]->denali_pi;
u32 *denali_phy = rk3399_ddr_publ[channel]->denali_phy;
- u32 *params_ctl = (u32 *)sdram_params->pctl_regs.denali_ctl;
- u32 *params_phy = (u32 *)sdram_params->phy_regs.denali_phy;
+ const u32 *params_ctl = sdram_params->pctl_regs.denali_ctl;
+ const u32 *params_phy = sdram_params->phy_regs.denali_phy;
u32 tmp, tmp1, tmp2;
u32 pwrup_srefresh_exit;
@@ -412,7 +412,7 @@ static void pctl_cfg(u32 channel,
copy_to_reg(&denali_ctl[1], &params_ctl[1],
sizeof(struct rk3399_ddr_pctl_regs) - 4);
write32(&denali_ctl[0], params_ctl[0]);
- copy_to_reg(denali_pi, (u32 *)&sdram_params->pi_regs.denali_pi[0],
+ copy_to_reg(denali_pi, &sdram_params->pi_regs.denali_pi[0],
sizeof(struct rk3399_ddr_pi_regs));
/* rank count need to set for init */
set_memory_map(channel, sdram_params);