summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorJamie Ryu <jamie.m.ryu@intel.com>2020-08-18 18:54:49 -0700
committerTim Wawrzynczak <twawrzynczak@chromium.org>2020-09-23 16:24:42 +0000
commit5b7daa224cb035f87c3b71105bb453849c7d54d4 (patch)
tree8c788d990f3a6c93be8c486cfdaa085eead8d2a1
parent81ab88b416caafc8a23b532e54dc4c1d0597f6af (diff)
downloadcoreboot-5b7daa224cb035f87c3b71105bb453849c7d54d4.tar.xz
soc/intel/tigerlake: Configure FSP UPDs for minimum assertion widths
Configure FSP UPDs for the chipset minimum assertion widths and power cycle duration per mainboard variants. * PchPmSlpS3MinAssert: SLP_S3 Minimum Assertion Width Policy * PchPmSlpS4MinAssert: SLP_S4 Minimum Assertion Width Policy * PchPmSlpSusMinAssert: SLP_SUS Minimum Assertion Width Policy * PchPmSlpAMinAssert: SLP_A Minimum Assertion Width Policy * PchPmPwrCycDur: PCH PM Reset Power Cycle Duration * Check to avoid violating the PCH EDS recommendation for the PchPmPwrCycDur setting. BUG=b:159108661 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Change-Id: I8180d95a2185c3786334e10613f47e77b7bc9d5f Reviewed-on: https://review.coreboot.org/c/coreboot/+/44557 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/soc/intel/tigerlake/chip.h53
-rw-r--r--src/soc/intel/tigerlake/fsp_params.c17
2 files changed, 70 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index dc8697b972..bcf71b1e62 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -389,6 +389,59 @@ struct soc_intel_tigerlake_config {
* Default 0. Setting this to 1 to check CPU replacement.
*/
uint8_t CpuReplacementCheck;
+
+ /*
+ * SLP_S3 Minimum Assertion Width Policy
+ * 1 = 60us
+ * 2 = 1ms
+ * 3 = 50ms (default)
+ * 4 = 2s
+ */
+ uint8_t PchPmSlpS3MinAssert;
+
+ /*
+ * SLP_S4 Minimum Assertion Width Policy
+ * 1 = 1s (default)
+ * 2 = 2s
+ * 3 = 3s
+ * 4 = 4s
+ */
+ uint8_t PchPmSlpS4MinAssert;
+
+ /*
+ * SLP_SUS Minimum Assertion Width Policy
+ * 1 = 0ms
+ * 2 = 500ms
+ * 3 = 1s
+ * 4 = 4s (default)
+ */
+ uint8_t PchPmSlpSusMinAssert;
+
+ /*
+ * SLP_A Minimum Assertion Width Policy
+ * 1 = 0ms
+ * 2 = 4s
+ * 3 = 98ms
+ * 4 = 2s (default)
+ */
+ uint8_t PchPmSlpAMinAssert;
+
+ /*
+ * PCH PM Reset Power Cycle Duration
+ * 0 = 4s (default)
+ * 1 = 1s
+ * 2 = 2s
+ * 3 = 3s
+ * 4 = 4s
+ *
+ * NOTE: Duration programmed in the PchPmPwrCycDur should never be smaller than the
+ * stretch duration programmed in the following registers:
+ * - GEN_PMCON_A.SLP_S3_MIN_ASST_WDTH (PchPmSlpS3MinAssert)
+ * - GEN_PMCON_A.S4MAW (PchPmSlpS4MinAssert)
+ * - PM_CFG.SLP_A_MIN_ASST_WDTH (PchPmSlpAMinAssert)
+ * - PM_CFG.SLP_LAN_MIN_ASST_WDTH
+ */
+ uint8_t PchPmPwrCycDur;
};
typedef struct soc_intel_tigerlake_config config_t;
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c
index 73a620d465..1c5490b0f8 100644
--- a/src/soc/intel/tigerlake/fsp_params.c
+++ b/src/soc/intel/tigerlake/fsp_params.c
@@ -10,6 +10,7 @@
#include <intelblocks/cse.h>
#include <intelblocks/lpss.h>
#include <intelblocks/mp_init.h>
+#include <intelblocks/pmclib.h>
#include <intelblocks/xdci.h>
#include <intelpch/lockdown.h>
#include <security/vboot/vboot_common.h>
@@ -331,6 +332,22 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
}
+ /* Apply minimum assertion width settings if non-zero */
+ if (config->PchPmSlpS3MinAssert)
+ params->PchPmSlpS3MinAssert = config->PchPmSlpS3MinAssert;
+ if (config->PchPmSlpS4MinAssert)
+ params->PchPmSlpS4MinAssert = config->PchPmSlpS4MinAssert;
+ if (config->PchPmSlpSusMinAssert)
+ params->PchPmSlpSusMinAssert = config->PchPmSlpSusMinAssert;
+ if (config->PchPmSlpAMinAssert)
+ params->PchPmSlpAMinAssert = config->PchPmSlpAMinAssert;
+
+ /* Set Power Cycle Duration */
+ if (config->PchPmPwrCycDur)
+ params->PchPmPwrCycDur = get_pm_pwr_cyc_dur(config->PchPmSlpS4MinAssert,
+ config->PchPmSlpS3MinAssert, config->PchPmSlpAMinAssert,
+ config->PchPmPwrCycDur);
+
/* EnableMultiPhaseSiliconInit for running MultiPhaseSiInit */
params->EnableMultiPhaseSiliconInit = 1;
mainboard_silicon_init_params(params);